Abstract: This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits. The encoder includes five subsections which generate a plurality of control signals. Each of the plurality of control signals is inputted into a separate one of five multiplexor circuits each of which also receives inputs representative of eight multiplicand bits in accordance with implementation of the Modified Booth Algorithm. Each of the five multiplexer circuits provides a plurality of outputs, each of the pluralities of outputs representing a separate partial product of the multiplier and multiplicand inputs. The partial products are inputted to an array of carry-save adders. The final stage of the adder network includes a carry-look-ahead adder which produces sixteen outputs which represent the product of the multiplier and the multiplicand.

Abstract: This disclosure relates to a programmable write-once, read-only semiconductor memory array which has an improved current source for each bit line and an improved current sink for each Word line. This programmable write-once, read-only semiconductor memory array utilizes a SCR (PNPN or NPNP) or the end of each Word line of the array to function as a current sink to minimize voltage drop on the Word line and a SCR (PNPN or NPNP) on each Bit line of the array for current sourcing purposes. This disclosure also relates to an integrated SCR (PNPN or NPNP) for use with a plurality of connected semiconductor devices to provide either a current sourcing or current sinking or drawing function for the plurality of connected semiconductor devices.

Abstract: Programmable array logic circuitry is disclosed wherein the outputs from a field programmable AND gate array are connected, non-programmably, to specified OR gates. For greater architectural and operational flexibility, registered outputs, internal feedback to the AND gate array, input/output pin interchangeability, and means for allowing performance of arithmetical, as well as logic, operations, are provided.