Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.

Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.

Abstract: A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC.

Abstract: An apparatus and method for minimizing the access time incurred when accessing redundant columns of a dynamic random access memory (DRAM) is herein disclosed. A pair of redundant columns is associated with a defective column. Each pair of redundant columns has a single redundant column decoder that provides access to the column data in the pair of redundant columns. The redundant column decoder is enabled by the column repair circuitry when it receives a column address signal indicating that a defective cell is to be accessed. When a defective column is accessed, the column data from the pair of associated redundant columns is read onto the IO lines as well as the data from the defective column. The three voltages are combined forming an IO signal and the complements of the three voltages are combined forming an IO-BAR signal. The sense amplifier determines the column data value based on the differential between the IO and IO-BAR signals.

Abstract: A multibank DRAM memory is described having individual row address strobe bar (RASB) and column address strobe bar (CASB) signals. Logically, only one row can be activated in each memory bank at a time and column access can be performed on one memory bank at a time. A token state machine is used to coordinate column access. In a first embodiment, two banks are utilized having respective asynchronous RASB signals transmitted from an external source. In a second embodiment, N DRAM memory banks are utilized having respective asynchronous internal RASB (IRASB) and internal CASB (ICASB) signals. A global RASB signal and a RASB identifier signal (RID) is used to generate the N IRASB and ICASB signals. The RID signal identifies a particular IRASB signal that is to be generated. The token state machine is operated in a round robin manner. In a third embodiment, the N DRAM memory banks are operated in a synchronous manner.

Abstract: The Vpp generator for use in a dynamic random access memory has a pump circuit and a voltage regulator. The voltage regulator controls the pump circuit such that the pumped up voltage has a maximum predetermined value. The prior art Vpp regulator sets the pumped up voltage, Vpp, to approximately a supply voltage, Vcc, plus the threshold voltage of a memory cell access transistor. This level becomes very high when the supply voltage, Vcc, is high and may overstress the devices. The present invention regulates the pumped up voltage, Vpp, at a substantially constant voltage level for high supply voltages. This level is safe and will not cause overstress.