Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.

Abstract: An apparatus can include a touch-up component. The touch-up component can detect a first charge parameter for a portion of memory of a memory system. The touch-up component can, subsequent to detecting the first charge parameter a particular time interval, detect a second charge parameter for the portion of memory. The touch-up component can determine a charge parameter change per time interval based on the first charge parameter, the second charge parameter, and the particular time interval. The touch-up component can perform a touch-up operation on the portion of memory at a particular time point based on the charge parameter change per time interval.

Abstract: The present disclosure relates to air assemblies having an inflation, a deflation, and a closed state for use with inflatable products, such as air mattresses. Specifically, the present disclosure relates to air assemblies where the configuration of the air assembly can be changed manually by a user by operating a directional control valve to inflate, deflate, or close the inflatable product. The directional control valve may also activate a pump in the inflation and deflation states and deactivate the pump in the closed state.

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: A planar transformer includes a magnetic core assembly, at least one printed circuit board and at least one winding module. The magnetic core assembly includes a first magnetic core and a second magnetic core. The at least one printed circuit board is disposed between the first magnetic core and the second magnetic core. The printed circuit board includes a first winding. The at least one winding module is disposed between the first magnetic core and the second magnetic core. The winding module includes a second winding and a plastic molding layer. At least a portion of the second winding is covered by the plastic molding layer. The at least one printed circuit board and the at least one winding module are individual components.

Abstract: Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

Abstract: Methods for creating a knowledge graph for a video are disclosed. Aspects include obtaining the video, processing the video to extract audio information and video information, and storing the extracted audio information and video information with a timestamp corresponding its occurrence in the video. Aspects also include creating a plurality of groups of the extracted audio information and video information based at least in part on the timestamps and extracting two or more keywords from each of the plurality of groups. Aspects further include identifying a relationship between the two or more keywords based on the extracted audio information and video information and creating a graph having a plurality of nodes and a plurality of links that connect a pair of nodes of the plurality of nodes. Each node corresponds to an extracted keyword and each link corresponds to the identified relationship between the pair of nodes.

Abstract: A micromirror assembly comprises a first position-limiting part, a micromirror chip, and a second position-limiting part that are stacked. The micromirror chip includes a fastening frame, a movable part, and a first cantilever, where the movable part is connected to the fastening frame by the first cantilever. The first position-limiting part and the second position-limiting part are separately connected to the fastening frame, the first position-limiting part and the second position-limiting part have a hollow area, and the hollow areas are opposite to the movable part. The first position-limiting part and the second position-limiting part are configured to absorb shock from a collision with the micromirror chip, and a projection of a collision part of the first position-limiting part on the micromirror chip intersects with a central axis of the first cantilever.

Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.

Abstract: The present disclosure relates to air assemblies having an inflation, a deflation, and a closed state for use with inflatable products, such as air mattresses. Specifically, the present disclosure relates to air assemblies where the configuration of the air assembly can be changed manually by a user by operating a directional control valve to inflate, deflate, or close the inflatable product. The directional control valve may also activate a pump in the inflation and deflation states and deactivate the pump in the closed state.

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.

Abstract: A memory device includes a memory array including wordlines and at least one string of cells. Each cell of the at least one string of cells is addressable by a respective wordline. The memory device further includes control logic, operatively coupled to the memory array, to perform operations including generating gate-induced drain leakage (GIDL) with respect to the at least one string of cells, and causing a grounding voltage to be applied to a set of wordlines to ground each cell of the at least one string of cells addressable by each wordline of the set of wordlines. The grounding voltage applied to the set of wordlines enables transport of positive charge carriers generated by the GIDL. In some embodiments, the positive charge carriers neutralize a buildup of negative charge carriers generated during a seeding phase of a program refresh operation.

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Abstract: A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

Abstract: A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.

Abstract: A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.

Abstract: A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.