Abstract: Embodiments of this application provide an optical fiber ferrule, where n rows of optical fiber holes are symmetrically distributed on a mating end face of the ferrule, n>=3, and n is an odd number. Based on the layout design of optical fiber holes on the optical fiber ferrule, this application provides an optical fiber connector that includes a plurality of rows of optical fiber holes and that is compatible with one row and a relatively small number of rows of optical fiber holes, so that an optical fiber connector with a large number of cores can be forward compatible with an optical fiber connector with a small number of cores, thereby improving expandability and compatibility of the optical fiber ferrule.

Abstract: Embodiments of this application provide an optical fiber ferrule, where n rows of optical fiber holes are symmetrically distributed on a mating end face of the ferrule, n>=3, and n is an odd number. Based on the layout design of optical fiber holes on the optical fiber ferrule, this application provides an optical fiber connector that includes a plurality of rows of optical fiber holes and that is compatible with one row and a relatively small number of rows of optical fiber holes, so that an optical fiber connector with a large number of cores can be forward compatible with an optical fiber connector with a small number of cores, thereby improving expandability and compatibility of the optical fiber ferrule.

Abstract: Embodiments of this application provide an optical fiber ferrule, where n rows of optical fiber holes are symmetrically distributed on a mating end face of the ferrule, n>=3, and n is an odd number. Based on the layout design of optical fiber holes on the optical fiber ferrule, this application provides an optical fiber connector that includes a plurality of rows of optical fiber holes and that is compatible with one row and a relatively small number of rows of optical fiber holes, so that an optical fiber connector with a large number of cores can be forward compatible with an optical fiber connector with a small number of cores, thereby improving expandability and compatibility of the optical fiber ferrule.

Abstract: Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.

Abstract: Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a microelectronics device includes a substrate and integrated circuitry variously formed in or on a front side of the substrate, where vias extend from the integrated circuitry to a back side of the substrate. A redistribution layer disposed on the back side includes a ring structure and a plurality of raised structures each extending from a recess portion that is surrounded by the ring structure. The ring structure and the plurality of raised structures provide contact surfaces for improved adhesion of dicing tape to the back side. In another embodiment, the plurality of raised structures includes dummification comprising dummy structures that are each electrically decoupled from any via extending through the substrate.

Abstract: A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads; and depositing solder on the accessible area of the contact pads. An apparatus including an integrated circuit substrate including a body having a nonplanar shape and a surface including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads.

Abstract: A method including forming a contact pad array on an integrated circuit substrate, the contact pad array including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads; and depositing solder on the accessible area of the contact pads. An apparatus including an integrated circuit substrate including a body having a nonplanar shape and a surface including a first plurality of contact pads and a second plurality of contact pads, wherein an accessible area of each of the first plurality of contact pads is different than an accessible area of each of the second plurality of contact pads.

Abstract: Die connections are described using different underfill types for different regions. In one example, a first electrically-non-conductive underfill paste (NCP) type is applied to an I/O region of a first die. A second NCP type is applied outside the I/O region of the first die, the second NCP type having more filler than the first NCP type, and the second die is bonded to a first die using the NCP.