Abstract: An optical receiver circuit is disclosed in which a number of electrical signals are processed to extract data encoded therein. The electrical signals may be compared during the process to selectively remove one or more waveforms from one or more corresponding electrical signals. Various data signals, each including one or more waveforms, may then be processed to extract the encoded data. The optical receiver circuit reduces, or eliminates, electrical offsets which may be present in one or more of the electrical signals to reduce corresponding errors in the encoded data signals.

Abstract: Consistent with the present disclosure, clock-and-data recovery (CDR) circuitry and driver circuitry are provided on a chip that is separate from the driver circuitry, thereby reducing the amount of power consumed by the driver circuitry and simplifying system design. In one example, timing of the ERZ signals is controlled by a feedback loop that adjusts the phase of a data carrying signal relative to a clock signal, such that the phase has a desired value. Timing of the ERZ signals may thus be adjusted to minimize errors.

Abstract: An improved integrated circuit (IC) layout is described that provides conductive pads on opposite sides of a substrate. The conductive pads provide for connectivity to the chip in different chip orientations. Accordingly, multiple chips having the same layout can be provided in a package, instead of providing each chip with a different layout. Since the same layout may be used for each chip, manufacturing costs are reduced.

Abstract: Consistent the present disclosure, a receive circuit is provided that includes a balanced detector portion and a transimpedance amplifier (TIA). The anode of one photodiode is connected to the cathode of the other by a bonding pad, which supplies the sum of the currents generated in each photodiode to an input of the TIA. Thus, the TIA may, for example, have a single input, as opposed to multiple inputs, thereby reducing the number of connections so that the photodiodes and the TIA may be integrated onto a smaller die. In addition, since there are few connections, fewer TIAs are required and differential stages are unnecessary. Power consumption is thus reduced, and, since the photodiode current is fed through one input to the TIA, fewer feedback resistors are required, thereby reducing thermal noise. In addition, since the anode of one photodiode is connected to the cathode of the other, the dark current generated in each flows in opposite directions, and is therefore effectively cancelled out.

Abstract: An optical receiver circuit is disclosed in which a number of electrical signals are processed to extract data encoded therein. The electrical signals may be compared during the process to selectively remove one or more waveforms from one or more corresponding electrical signals. Various data signals, each including one or more waveforms, may then be processed to extract the encoded data. The optical receiver circuit reduces, or eliminates, electrical offsets which may be present in one or more of the electrical signals to reduce corresponding errors in the encoded data signals.

Abstract: A delay line for deployment in an equalizer to insert a delay in a signal received by the delay line employs a plurality of cascaded delay stages where the delay per stage provided by an active unit-gain amplifier in each stage that provides sufficient impedance mismatch between the delay stages without substantial deterioration of the frequency response of the client signal undergoing deterioration of the frequency response of the client signal undergoing delay.

Abstract: Consistent with the present disclosure, a “dummy” transimpedance amplifier (dummy TIA) is provided on a substrate along with one or more other transimpedance amplifiers (TIAs) that are connected to photodiodes and output voltage signals for further processing. Typically, the dummy TIA is not connected to a photodiode and does not supply a useful output. The dummy TIA, however, is subject to the same processing and temperature variations as the other TIAs, and, as a result, the voltage on the dummy TIA inverting input will be the same or substantially the same as that of the other TIAs. Thus, by sensing the dummy TIA inverting input voltage, an appropriate photodiode bias can be obtained without direct measurement of the voltage on the inverting inputs of the other TIAs.

Abstract: Consistent with the present disclosure, clock-and-data recovery (CDR) circuitry and driver circuitry are provided on a chip that is separate from the driver circuitry, thereby reducing the amount of power consumed by the driver circuitry and simplifying system design. In one example, timing of the ERZ signals is controlled by a feedback loop that adjusts the phase of a data carrying signal relative to a clock signal, such that the phase has a desired value. Timing of the ERZ signals may thus be adjusted to minimize errors.

Abstract: Consistent with the present disclosure, a “dummy” transimpedance amplifier (dummy TIA) is provided on a substrate along with one or more other transimpedance amplifiers (TIAs) that are connected to photodiodes and output voltage signals for further processing. Typically, the dummy TIA is not connected to a photodiode and does not supply a useful output. The dummy TIA, however, is subject to the same processing and temperature variations as the other TIAs, and, as a result, the voltage on the dummy TIA inverting input will be the same or substantially the same as that of the other TIAs. Thus, by sensing the dummy TIA inverting input voltage, an appropriate photodiode bias can be obtained without direct measurement of the voltage on the inverting inputs of the other TIAs.

Abstract: An improved integrated circuit (IC) layout is described that provides conductive pads on opposite sides of a substrate. The conductive pads provide for connectivity to the chip in different chip orientations. Accordingly, multiple chips having the same layout can be provided in a package, instead of providing each chip with a different layout. Since the same layout may be used for each chip, manufacturing costs are reduced.

Abstract: A delay line for deployment in an equalizer to insert a delay in a signal received by the delay line employs a plurality of cascaded delay stages where the delay per stage provided by an active unit-gain amplifier in each stage that provides sufficient impedance mismatch between the delay stages without substantial deterioration of the frequency response of the client signal undergoing deterioration of the frequency response of the client signal undergoing delay.

Abstract: A circuit that increases the efficiency of a radio frequency mobile telephone unit is disclosed. When the signal strength between the base station and the mobile unit is below a predetermined signal strength level, the power amplifier is turned on and the transmitter circuit of the mobile unit fully amplifies the RF signal. However, when the signal strength between the mobile telephone unit and the base station is above a predetermined signal strength level, the power amplifier is deactivated and bypassed from the transmitter circuitry, thereby conserving the battery power of the mobile unit.

Abstract: A feedforward linearizer includes a signal cancellation circuit and an error cancellation circuit. The signal cancellation circuit includes a tap delay line, that delay the input signal by a predetermined time delay so as to provide several delayed versions of the input signal. Each delayed version of the input signal is weighted by a tap coefficient. The weighted signals are then added together and fed to the power amplifier. The tap coefficients are derived such that the signals traveling through the upper and lower branch of the signal cancellation loop are aligned and that the output signal of the power amplifier is equalized.

Abstract: A feedforward linearizer for amplifying an input signal comprises a signal cancellation circuit which has a first branch and a second branch. A first amplifier provided in the first branch receives the input signal intended to be amplified and generates an output signal received by a signal cancellation vector modulator. A signal cancellation adder receives the signal generated by the signal cancellation vector modulator and the input signal via the second branch and provides an error signal. The feedforward linearizer also comprises an error cancellation circuit that has a first branch and a second branch. An error cancellation adder in the first branch receives the output signal provided by the first amplifier and generates the output signal of the linearizer. An error cancellation vector modulator in the second branch receives an error signal provided by the signal cancellation adder and provides an error adjusted signal to a second auxiliary amplifier.

Abstract: A cellular communication signal receiver receives a desired signal in the presence of at least one co-channel interference signal. The receiver comprises a channel estimator configured to receive a plurality of training signal samples to estimate the finite impulse response to the desired signal and the co-channel interference signal. The finite impulse response estimates having a predetermined number of channel taps defining the length of the desired channel and the length of co-channel interference channel. A Viterbi decoder is coupled to the channel estimator, and configured to receive the desired and co-channel interference signals. The channel estimator generates channel tap estimates. A power calculator is coupled to the channel estimator and configured to estimate the power of the estimated channel taps.

Abstract: A feedforward linearizer for amplifying an input signal comprises a signal cancellation circuit which has a first branch and a second branch. A first amplifier provided in the first branch receives the input signal intended to be amplified and generates an output signal received by a signal cancellation vector modulator. A signal cancellation adder receives the signal generated by the signal cancellation vector modulator and the input signal via the second branch and provides an error signal. The feedforward linearizer also comprises an error cancellation circuit that has a first branch and a second branch. An error cancellation adder in the first branch receives the output signal provided by the first amplifier and generates the output signal of the linearizer. An error cancellation vector modulator in the second branch receives an error signal provided by the signal cancellation adder and provides an error adjusted signal to a second auxiliary amplifier.