Patents by Inventor Huang-Kui CHEN
Huang-Kui CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230371281Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Kui CHEN, Guan-Jie Shen
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Patent number: 11793003Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.Type: GrantFiled: July 10, 2020Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Kui Chen, Guan-Jie Shen
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Patent number: 11653503Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: GrantFiled: August 28, 2020Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Woan-Yun Hsiao, Huang-Kui Chen, Tzong-Sheng Chang, Ya-Chin King, Chrong-Jung Lin
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Publication number: 20220013582Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure, a conductor layer over and in contact with the layer of dielectric material and above the S/D contact structure, and an interconnect structure over and in contact with the conductor layer.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Kui CHEN, Guan-Jie SHEN
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Patent number: 11152355Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.Type: GrantFiled: July 29, 2019Date of Patent: October 19, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fan-Shuen Meng, Huang-Kui Chen, Min-Yann Hsieh
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Patent number: 11114336Abstract: In a method of manufacturing a semiconductor device, a first source/drain structure is formed over a substrate, one or more first insulating layers are formed over the first source/drain structure, a first opening is formed in the one or more first insulating layers, the first opening is filled with a first conductive material to form a first lower contact in contact with the first source/drain structure, one or more second insulating layers are formed over the first lower contact, a second opening is formed in the one or more second insulating layers to at least partially expose the first lower contact, a first liner layer is formed on at least a part of an inner side face of the second opening, and the second opening is filled with a second conductive material to form a first upper contact in contact with the first lower contact without the first liner layer.Type: GrantFiled: November 20, 2019Date of Patent: September 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Huang-Kui Chen
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Publication number: 20200395411Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: ApplicationFiled: August 28, 2020Publication date: December 17, 2020Inventors: Woan-Yun HSIAO, Huang-Kui CHEN, Tzong-Sheng CHANG, Ya-Chin KING, Chrong-Jung LIN
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Patent number: 10763305Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: GrantFiled: September 18, 2018Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Woan-Yun Hsiao, Huang-Kui Chen, Tzong-Sheng Chang, Ya-Chin King, Chrong-Jung Lin
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Publication number: 20200176309Abstract: In a method of manufacturing a semiconductor device, a first source/drain structure is formed over a substrate, one or more first insulating layers are formed over the first source/drain structure, a first opening is formed in the one or more first insulating layers, the first opening is filled with a first conductive material to form a first lower contact in contact with the first source/drain structure, one or more second insulating layers are formed over the first lower contact, a second opening is formed in the one or more second insulating layers to at least partially expose the first lower contact, a first liner layer is formed on at least a part of an inner side face of the second opening, and the second opening is filled with a second conductive material to form a first upper contact in contact with the first lower contact without the first liner layer.Type: ApplicationFiled: November 20, 2019Publication date: June 4, 2020Inventor: Huang-Kui CHEN
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Publication number: 20190355716Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.Type: ApplicationFiled: July 29, 2019Publication date: November 21, 2019Inventors: Fan-Shuen Meng, Huang-Kui Chen, Min-Yann Hsieh
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Patent number: 10366982Abstract: The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.Type: GrantFiled: January 31, 2018Date of Patent: July 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fan-Shuen Meng, Huang-Kui Chen, Min-Yann Hsieh
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Publication number: 20190164957Abstract: The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; depositing an interlayer dielectric (ILD) layer on the source and drain; patterning the ILD layer to form a first contact hole and a second contact hole aligning with the source and drain, respectively; forming a dielectric material layer in the first contact hole; and forming a first conductive feature and a second conductive feature in the first and second contact holes, respectively.Type: ApplicationFiled: January 31, 2018Publication date: May 30, 2019Inventors: Fan-Shuen Meng, Huang-Kui Chen, Min-Yann Hsieh
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Publication number: 20190035850Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: ApplicationFiled: September 18, 2018Publication date: January 31, 2019Inventors: Woan-Yun HSIAO, Huang-Kui CHEN, Tzong-Sheng CHANG, Ya-Chin KING, Chrong-Jung LIN
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Patent number: 10090360Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: GrantFiled: October 16, 2015Date of Patent: October 2, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Woan-Yun Hsiao, Ya-Chin King, Chrong-Jung Lin, Huang-Kui Chen, Tzong-Sheng Chang
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Patent number: 9484346Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a first and a second surface, and an interlayer dielectric (ILD) defining a first metal gate and a second metal gate over the first and second surface, respectively. The first and second metal gate include a first SAC hard mask and a second SAC hard mask, respectively, wherein the first the second SAC hard mask have opposite stress to channel regions underneath the first and second metal gate, respectively. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming metal gate recesses, forming metal gates and SAC hard masks in the metal gate recesses, respectively.Type: GrantFiled: October 15, 2014Date of Patent: November 1, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTDInventor: Huang-Kui Chen
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Patent number: 9449963Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first capacitor structure. The first capacitor structure includes a fin structure formed over a substrate and a first gate structure formed over the substrate. In addition, a first portion of the first gate structure overlaps with a portion of the fin structure. The first capacitor structure further includes a first hard mask structure formed over the first portion of the first gate structure and a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure. The first capacitor structure further includes a first contact formed on a second portion of the first gate structure. In addition, the first contact is in direct contact with the second portion of the first gate structure.Type: GrantFiled: July 3, 2014Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Huang-Kui Chen
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Publication number: 20160240775Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.Type: ApplicationFiled: October 16, 2015Publication date: August 18, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Woan-Yun HSIAO, Ya-Chin KING, Chrong-Jung LIN, Huang-Kui CHEN, Tzong-Sheng CHANG
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Patent number: 9385235Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure also includes a gate electrode formed over the fin structure, and the gate electrode has a grid-like pattern when seen from a top-view.Type: GrantFiled: May 30, 2014Date of Patent: July 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Huang-Kui Chen
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Publication number: 20160111425Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a first and a second surface, and an interlayer dielectric (ILD) defining a first metal gate and a second metal gate over the first and second surface, respectively. The first and second metal gate include a first SAC hard mask and a second SAC hard mask, respectively, wherein the first the second SAC hard mask have opposite stress to channel regions underneath the first and second metal gate, respectively. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming metal gate recesses, forming metal gates and SAC hard masks in the metal gate recesses, respectively.Type: ApplicationFiled: October 15, 2014Publication date: April 21, 2016Inventor: HUANG-KUI CHEN
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Publication number: 20160005731Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first capacitor structure. The first capacitor structure includes a fin structure formed over a substrate and a first gate structure formed over the substrate. In addition, a first portion of the first gate structure overlaps with a portion of the fin structure. The first capacitor structure further includes a first hard mask structure formed over the first portion of the first gate structure and a first conductive structure formed on the first hard mask structure over the first portion of the first gate structure. The first capacitor structure further includes a first contact formed on a second portion of the first gate structure. In addition, the first contact is in direct contact with the second portion of the first gate structure.Type: ApplicationFiled: July 3, 2014Publication date: January 7, 2016Inventor: Huang-Kui CHEN