Patents by Inventor Huang-Sheng Lin
Huang-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162321Abstract: A semiconductor structure includes a substrate, a dielectric wall, and two device units. The dielectric wall has two side surfaces opposite to each other. The two device units are respectively formed at the two side surfaces of the dielectric wall. Each of the device units includes channel features, a gate feature and a dielectric filler unit. The channel features are disposed on a corresponding one of the side surfaces of the dielectric wall, and spaced apart from each other. The gate feature is formed around the channel features and disposed on the corresponding one of the side surfaces of the dielectric wall. The dielectric filler unit includes a plurality of first dielectric fillers, each of which is disposed between the dielectric wall and a corresponding one of the channel features. The first dielectric fillers have a dielectric constant greater than that of the dielectric wall.Type: ApplicationFiled: February 22, 2023Publication date: May 16, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Huang-Chao CHANG, Ta-Chun LIN, Chun-Sheng LIANG, Jhon-Jhy LIAW
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Publication number: 20240088149Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.Type: ApplicationFiled: February 15, 2023Publication date: March 14, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Chun LIN, Ming-Heng TSAI, Huang-Chao CHANG, Chun-Sheng LIANG, Chih-Hao CHANG, Jhon Jhy LIAW
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Patent number: 11855010Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.Type: GrantFiled: August 6, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shan-Yu Huang, Shih-Chang Chen, Hsiao-Wen Chung, Yilun Chen, Huang-Sheng Lin
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Publication number: 20230402335Abstract: A first die includes a plurality of first transistors. A first seal ring surrounds the first die in a top view. A second die that a plurality of second transistors. A second seal ring surrounds the second die in the top view. A plurality of conductive elements extends into both the first die and the second die in the top view. The conductive elements electrically interconnect the first die with the second die. A third seal ring surrounds, in the top view, the first die, the second die, and the conductive elements.Type: ApplicationFiled: June 13, 2022Publication date: December 14, 2023Inventors: Shan-Yu Huang, Yilun Chen, Huang-Sheng Lin
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Publication number: 20230402406Abstract: An array of dies is formed over a substrate. Each of the dies contains a plurality of functional transistors. A plurality of first seal rings each surround a respective one of the dies in a top view. The first seal rings define a plurality of corner regions that are disposed outside of the first seal rings and between corners of respective subsets of the dies. A plurality of structures is disposed within the corner regions. The structures include test structures, dummy structures, process monitor patterns, alignment marks, or overlay marks. Electrical interconnection elements are disposed between each pair of adjacent dies in the array of dies in the top view. The electrical interconnection elements electrically interconnect the dies in the array with one another. A second seal ring surrounds the array of dies, the first seal rings, and the structures in the top view.Type: ApplicationFiled: June 14, 2022Publication date: December 14, 2023Inventors: Shan-Yu Huang, Shih-Chang Chen, Yilun Chen, Huang-Sheng Lin
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Publication number: 20230369148Abstract: A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.Type: ApplicationFiled: July 19, 2023Publication date: November 16, 2023Inventors: Shan-Yu Huang, Hsiao-Wen Chung, Yi-Lun Chen, Huang-Sheng Lin
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Publication number: 20230317638Abstract: A semiconductor structure includes a first circuit region; a first inner seal ring at least partially surrounding the first circuit region; and an outer seal ring at least partially surrounding the first inner seal ring. The outer seal ring includes a first corner and a substantially triangular corner seal ring (CSR) structure at the first corner. The first inner seal ring includes a second corner adjacent to and spaced away from the CSR structure. The semiconductor structure further includes a first region between a first side of the first corner and a first side of the second corner that is parallel to the first side of the first corner, and multiple functional patterns in the first region.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventors: Shan-Yu Huang, Yilun Chen, Huang-Sheng Lin
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Patent number: 11728229Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.Type: GrantFiled: June 2, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shan-Yu Huang, Hsiao-Wen Chung, Yi-Lun Chen, Huang-Sheng Lin
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Publication number: 20230041160Abstract: A semiconductor structure is provided. The semiconductor structure includes two circuit regions, two inner seal rings, an outer seal ring, a first redundant region, and an electrical circuit. Each of the inner seal rings surrounding one of the circuit regions. The outer seal ring is disposed around the inner seal rings, and each of the inner seal rings contacts the outer seal ring at different interior corners of the outer seal ring. The first redundant region is located between at least one of the inner seal rings and the outer seal ring. The electrical circuit is formed in the first redundant region and electrically connected to at least one of the circuit regions.Type: ApplicationFiled: August 6, 2021Publication date: February 9, 2023Inventors: Shan-Yu HUANG, Shih-Chang CHEN, Hsiao-Wen CHUNG, Yilun CHEN, Huang-Sheng LIN
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Publication number: 20220310464Abstract: A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.Type: ApplicationFiled: June 2, 2021Publication date: September 29, 2022Inventors: Shan-Yu Huang, Hsiao-Wen Chung, Yi-Lun Chen, Huang-Sheng Lin
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Patent number: 8626580Abstract: A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.Type: GrantFiled: August 31, 2006Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chi Chin, Shouh-Dauh Fred Lin, Lawrence Chen, Chun-Mai Liu, Huang-Sheng Lin
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Patent number: 7378720Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.Type: GrantFiled: April 3, 2007Date of Patent: May 27, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen
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Patent number: 7323784Abstract: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.Type: GrantFiled: March 17, 2005Date of Patent: January 29, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ho-Yin Yiu, Fu-Jier Fan, Yu-Jui Wu, Aaron Wang, Hsiang-Wei Wang, Huang-Sheng Lin, Ming-Hsien Chen, Ruey-Yun Shiue
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Publication number: 20070187845Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.Type: ApplicationFiled: April 3, 2007Publication date: August 16, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen
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Publication number: 20070156526Abstract: A semiconductor coupon-service system, includes a coupon-service module for managing a semiconductor service; a coupon generator, in connection with the semiconductor service, for generating a coupon associated with the semiconductor service; and a coupon maintainer, in connection with the semiconductor service, for processing coupon operations associated with the coupon.Type: ApplicationFiled: August 31, 2006Publication date: July 5, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Chi CHIN, Shouh-Dauh Fred LIN, Lawrence CHEN, Chun-Mai LIU, Huang-Sheng LIN
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Patent number: 7202550Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.Type: GrantFiled: November 8, 2004Date of Patent: April 10, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen
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Publication number: 20060257790Abstract: Described is a semiconductor device structure with improved iso-dense bias and methods of producing thereof. Non-functional patterns may be added to an integrated circuit layout design. These patterns may be located next to an isolated transistor or an array of densely-packed transistors in order to mitigate the iso-dense bias effects. Furthermore, the patterns can take on a variety of geometric shapes and sizes.Type: ApplicationFiled: May 16, 2005Publication date: November 16, 2006Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: LI-CHUN TIEN, MI-CHANG CHANG, HUANG-SHENG LIN, YU-CHYI HARN
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Publication number: 20060208360Abstract: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.Type: ApplicationFiled: March 17, 2005Publication date: September 21, 2006Inventors: Ho-Yin Yiu, Fu-Jier Fan, Yu-Jui Wu, Aaron Wang, Hsiang-Wei Wang, Huang-Sheng Lin, Ming-Hsien Chen, Ruey-Yun Shiue
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Publication number: 20050263855Abstract: A semiconductor die having an integrated circuit region formed in a substrate comprises at least one die-corner-circuit-forbidden (DCCF) region disposed in the substrate, proximate to the integrated circuit region; and at least one registration feature formed within the at least one DCCF region. The at least one registration feature comprises a structure selected from the group consisting of a laser fuse mark, an alignment mark, and a monitor mark.Type: ApplicationFiled: November 8, 2004Publication date: December 1, 2005Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-min Fu, Huang-Sheng Lin, Yu-Chyi Harn, Hsien-Wei Chen