Abstract: A computer system arranged for faster processing operations by providing a stack cache in internal register memory. A full stack is provided in main memory. The stack cache provides a cache representation of part of the main memory stack. Stack relative addresses contained in procedure instructions are converted to absolute main memory stack addresses. A subset of the absolute main memory stack address is used to directly address the stack cache when a "hit" is detected. Otherwise, the main memory stack is addressed. The stack cache is implemented as a set of contiguously addressable registers. Two stack pointers are used to implement allocation space in the stack as a circulating buffer. Cache hits are detected by comparing the absolute stack address to the contents of the two circular buffer pointers. Space for a procedure is allocated upon entering a procedure. The amount of space to allocate is stored in the first instruction. Space is deallocated when a procedure is terminated.

Abstract: Arrangement and method for avoiding the processing time associated with executing branch instructions in a computer. An instruction fetch unit appends a next instruction address field to each instruction it passes it via an instruction cache to an instruction execution unit. The fetch unit decodes the present instruction being read and the next sequential instruction in main memory. If neither instruction is a branch instruction, the next address field is set to the address of the next sequential instruction. If the present instruction is a branch, the next instruction address field is set to the branch address contained in the present instruction. If neither of these cases are true and the next sequential instruction from main memory is a branch, the next instruction address field is set to the branch address of this instruction. The execution unit uses the next instruction address to access instructions from the instruction cache. Thus, execution of branch instructions by the execution unit are avoided.