Patents by Inventor Hubertus Gerardus Hendrikus Vermeulen
Hubertus Gerardus Hendrikus Vermeulen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130070613Abstract: Systems and methods for testing a communications network having a central bus guardian (CBG) to detect a faulty condition associated with the CBG are described. In one embodiment, a method for testing a communications network having a CBG to detect a faulty condition associated with the CBG includes supplying a communications schedule to the CBG, causing test data to be transmitted between different buses that are connected to the CBG according to the communications schedule, and determining the faulty condition associated to with the CBG based on whether or not the test data is received according to the communications schedule. Other embodiments are also described.Type: ApplicationFiled: September 21, 2011Publication date: March 21, 2013Applicant: NXP B.V.Inventors: ABHIJIT KUMAR DEB, SUJAN PANDEY, HUBERTUS GERARDUS HENDRIKUS VERMEULEN
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Publication number: 20130073764Abstract: Central bus guardians (CBGs) and methods for operating a CBG are described. In one embodiment, a method for operating a CBG includes performing race arbitration among the buses connected to the CBG to select a winner bus for a time slot, and selectively forwarding data received at the CBG from the winner bus to a destination bus in the time slot based on whether the winner bus or the destination bus has a connection to an external network with respect to the application network and whether a communications device connected to the winner bus or the destination bus performs a critical function. Other embodiments are also described.Type: ApplicationFiled: September 21, 2011Publication date: March 21, 2013Applicant: NXP B.V.Inventors: ABHIJIT KUMAR DEB, HUBERTUS GERARDUS HENDRIKUS VERMEULEN, SUJAN PANDEY
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Publication number: 20130070783Abstract: An invention for generating a slot table entry address for a communications device of a communications network includes a method that involves processing a slot counter value according to a configuration setting value to produce a processed slot counter value, the slot counter value identifying a time slot of data communications of the communications network, masking a cycle counter value according to the configuration setting value to generate a masked cycle counter value, where the cycle counter value identifies a communications cycle containing the time slot, and processing the processed slot counter value and the masked cycle counter value to generate a slot table entry address such that a corresponding slot table entry of the time slot of the communications cycle in a slot table is accessed by the communications device at the slot table entry address.Type: ApplicationFiled: September 21, 2011Publication date: March 21, 2013Applicant: NXP B.V.Inventors: HUBERTUS GERARDUS HENDRIKUS VERMEULEN, ABHIJIT KUMAR DEB, SUJAN PANDEY
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Publication number: 20130070782Abstract: Systems and methods for encoding a slot table for a communications controller of a communications network are described. In one embodiment, a method for encoding a slot table for a communications controller of a communications network includes classifying branches of the communications network that are connected to the communications controller into at least one group, where each of the at least one group includes multiple branches, and generating a slot table entry for a time slot for accessing the communications network through the communications controller based on the at least one group. Other embodiments are also described.Type: ApplicationFiled: September 21, 2011Publication date: March 21, 2013Applicant: NXP B.V.Inventors: HUBERTUS GERARDUS HENDRIKUS VERMEULEN, SUJAN PANDEY, ABHIJIT KUMAR DEB
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Publication number: 20120250587Abstract: Duplex communications are facilitated. In connection with various example embodiments, current sources are used to drive transistor-based circuits coupled across a first resistive circuit, to send signals on a communications medium. While driving the transistor-based circuits, the current sources are used to drive reference transistor-based circuits coupled across a second resistive circuit. A differential output signal based upon a power-related value across the first resistive circuit, less a power-related value across the second resistive circuit. This differential output signal characterizes a power-related value corresponding to a received signal on the communications medium, as gleaned from a total signal corresponding to both transmitted and received signals, less a signal corresponding to the transmitted signal.Type: ApplicationFiled: March 30, 2011Publication date: October 4, 2012Inventors: Sujan Pandey, Hubertus Gerardus Hendrikus Vermeulen, Abhijit Kumar Deb
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Publication number: 20120054207Abstract: The present invention relates to a circuit for sorting a set of data values, the circuit comprising a first set of p+q registers for storing the p+q largest data values of the set of data values including p statistical outliers; a second set of p+q registers for storing the p+q smallest data values of the set of data values including p statistical outliers, wherein p is a non-negative integer and q is a positive integer; a controller coupled to each register in said first and second sets, said controller being arranged to: receive the set of data values and for each data value obtain a comparison result of the data value with the respective data values in each of said registers; and update said registers as a function of said comparison results; the circuit further comprising a data processing circuit coupled to at least the q registers in said first and second sets, which for instance may be used to produce an average value of the data values stored in said q registers in response to the controller.Type: ApplicationFiled: July 26, 2011Publication date: March 1, 2012Applicant: NXP B.V.Inventors: Hubertus Gerardus Hendrikus Vermeulen, Jan Staschulat, Andre Krijn Nieuwland, Elisabeth Francisca Maria Steffens
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Publication number: 20110194458Abstract: Disclosed is a method of switching modes in a serial data communication network comprising a plurality of interconnected nodes, each of said nodes comprising a plurality of mode-dependent configurations, the method including, during a first mode, issuing an instruction to said nodes, said instruction identifying a next mode of the data communication network; terminating said first mode; and following said termination, reconfiguring each of said nodes in accordance with the configuration corresponding to said next mode identified by said instruction. A serial data communication network implementing such a method is also disclosed.Type: ApplicationFiled: December 21, 2010Publication date: August 11, 2011Applicant: NXP B.V.Inventors: Andre Krijn NIEUWLAND, Jan STASCHULAT, Elisabeth Francisca Maria STEFFENS, Hubertus Gerardus Hendrikus VERMEULEN
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Publication number: 20110179316Abstract: A data processing system 100 comprising a monitor 120 is provided and corresponding system-on-chip, method for monitoring and computer program product. The data processing system comprises multiple processing devices 104, 106, 116, 116 and a monitor 120. The monitor is configured to monitor characteristics of the data streams 102, 112, occurring among the plurality of data processing devices. The monitor comprises a means to determine whether a system characteristic substantially deviates from an expected system characteristic and to raise an anomaly signal if so. The system characteristic depends on the first characteristic and the second characteristic. In this way the monitor increases robustness by monitoring for problems related to deviations in the relation between multiple data streams.Type: ApplicationFiled: September 22, 2009Publication date: July 21, 2011Inventors: Marc Jeroen Geuzebroek, Andre Krijn Nieuwland, Hubertus Gerardus Hendrikus Vermeulen
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Publication number: 20100264932Abstract: An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown.Type: ApplicationFiled: August 9, 2006Publication date: October 21, 2010Applicant: NXP B.V.Inventors: Erik Jan Marinissen, Sandeepkumar Goel, Andre Krijn Nieuwland, Hubertus Gerardus Hendrikus Vermeulen, Hendrikus Petrus Elisabeth Vranken
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Publication number: 20100223515Abstract: An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.Type: ApplicationFiled: August 9, 2006Publication date: September 2, 2010Applicant: NXP B.V.Inventors: Andre Krijn Nieuwland, Sandeepkumar Goel, Erik Jan Marinissen, Hubertus Gerardus Hendrikus Vermeulen, Hendrikus Petrus Elisabeth Vranken
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Publication number: 20100169896Abstract: An electronic device is provided which comprises a plurality of processing units (IP; IP1-IP4), an interconnect (IPCU; N) for coupling the processing units (IP; IP1-IP4) to enable a communication between the processing units (IP; IP1-IP4) and at least one event monitor (EM) for detecting events in the communication in the electronic device. The electronic device furthermore comprises a first controller unit for controlling the interconnect (IPCU; N) according to one or more of the events detected by the at least one event monitor (EM).Type: ApplicationFiled: August 7, 2007Publication date: July 1, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Martinus Theodorus Bennebroek, Kees Gerard Willem Goossens, Hubertus Gerardus Hendrikus Vermeulen
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Patent number: 7475317Abstract: A method of generating digital test patterns for testing a number of wiring interconnects is described. A first set of test patterns is generated; the number of test patterns in the first set is related to said number of wiring interconnects, and defines a first set of code words. From the first set of code words, a second set of code words is selected. The number of code words in the second set is equal to said number of wiring interconnects, and the selection of the second set of code words is such that the sum of the transition counts for the code words in the second set is minimized.Type: GrantFiled: May 19, 2004Date of Patent: January 6, 2009Assignee: Koninklijke Philips Electronics N.V.Inventors: Erik Jan Marinissen, Hubertus Gerardus Hendrikus Vermeulen, Hendrik Dirk Lodewijk Hollmann
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Patent number: 7076709Abstract: An electronic circuit has a plurality of sub-circuits. Clock gate circuits supply gated clock signals to data storage elements of the sub-circuits. The clock gate circuits have gate inputs for receiving gate signals that commands blocking passage of the clock signal. Data can be transferred between data storage elements between two of the subcircuits. A detector circuit flags invalid data in the data storage element of the second one of the sub-circuits. The detector circuit has a flag storage element arranged to set a flag when the clock gate circuit of the second one of the sub-circuits passes the clock signal for the second one of the sub-circuits after the clock gate of the first one of the sub-circuits has blocked the clock signal for the first one of the sub-circuits. The flag indicates the relative phase of the clocks signals of different sub-circuits when the clocks are stopped. The flag is used to invalidate data in the data storage element of the second one of the sub-circuits.Type: GrantFiled: December 23, 2002Date of Patent: July 11, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Hubertus Gerardus Hendrikus Vermeulen, Sandeep Kumar Goel
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Patent number: 6988230Abstract: An electronic device has a plurality of subdevices with each subdevice coupled to a test interface. The test interfaces are arranged in a chain of test interfaces by coupling the TDO contact of a predecessor test interface to the TDI contact of a successor test interface in the chain. In addition, at its beginning, the chain is extended with a boundary scan compliant test interface for testing other parts of electronic device. Both the TDO contact of the last test interface in the chain as well as the TDO contact of test interface are coupled to a bypass multiplexer, thus yielding two possible routes from test data input to test data output: through the full chain or through test interface only. Consequently, electronic device can be tested or debugged as a macro device or as a collection of subdevices.Type: GrantFiled: September 17, 2002Date of Patent: January 17, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Hubertus Gerardus Hendrikus Vermeulen, Thomas Franciscus Waayers, Guillaume Elisabeth Andreas Lousberg
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Publication number: 20030079166Abstract: An electronic device (100) has a plurality of subdevices (120a, 120b) with each subdevice (120a; 120b) coupled to a test interface (140a; 140b). The test interfaces (140a, 140b) are arranged in a chain of test interfaces (140) by coupling the TDO contact (142b) of a predecessor test interface (140a) to the TDI contact (141b) of a successor test interface (140b) in the chain (140). In addition, at its beginning, the chain (140) is extended with a boundary scan compliant test interface (160) for testing other parts of electronic device (100). Both the TDO contact (142b) of the last test interface (140b) in the chain (140) as well as the TDO contact (162) of test interface (160) are coupled to a bypass multiplexer (102), thus yielding two possible routes from test data input (110) to test data output (112): through the full chain (140, 160) or through test interface (160) only. Consequently, electronic device (100) can be tested or debugged as a macro device or as a collection of subdevices (120a, 120b).Type: ApplicationFiled: September 17, 2002Publication date: April 24, 2003Inventors: Hubertus Gerardus Hendrikus Vermeulen, Thomas Franciscus Waayers, Guillaume Elisabeth Andreas Lousberg