Abstract: An example of an isolation sensor package is disclosed to include a first Integrated Circuit (IC) chip and a second IC chip. The first IC chip may include an input interface circuit that receives an input signal from a first input signal terminal and a second input signal terminal, where the input signal ranges between a first positive voltage and a first negative voltage. The first IC chip may further include a negative voltage generator that generates a second negative voltage, a level shifter that receives an output of the input interface circuit and generates a modified signal having a voltage level between a ground voltage provided to the ground terminal and a second positive voltage that is present at a voltage supply terminal. The first IC chip may further produce a signal based on the modified signal generated by the level shifter.

Abstract: According to embodiments of the present invention, a flip-flop circuit is provided. The flip-flop circuit includes a first stage circuit and a second stage circuit, wherein each of the first stage circuit and the second stage circuit is operable in two modes of operation, and a driver arrangement, wherein the first stage circuit includes a first transistor and a first non-volatile memory cell connected to each other, wherein the second stage circuit includes a second transistor and a second non-volatile memory cell connected to each other, and wherein the driver arrangement is configured, at a clock level, to drive the first stage circuit in one of the two modes of operation to access the first non-volatile memory cell and, at the clock level, to drive the second stage circuit in the other of the two modes of operation to access the second non-volatile memory cell.

Abstract: According to various embodiments, there is provided a memory device including at least one sense amplifier having a first side and a second side, wherein the second side opposes the first side; a first array including a plurality of memory cells arranged at the first side; a second array including a plurality of memory cells arranged at the second side; a first row including a plurality of mid-point reference units arranged at the first side; and a second row including a plurality of mid-point reference units arranged at the second side, wherein each mid-point reference unit of the first row is configured to generate a first reference voltage, and wherein each mid-point reference unit of the second row is configured to generate a second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the first array based on the second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the second arra

Abstract: According to embodiments of the present invention, a flip-flop circuit is provided. The flip-flop circuit includes a first stage circuit and a second stage circuit, wherein each of the first stage circuit and the second stage circuit is operable in two modes of operation, and a driver arrangement, wherein the first stage circuit includes a first transistor and a first non-volatile memory cell connected to each other, wherein the second stage circuit includes a second transistor and a second non-volatile memory cell connected to each other, and wherein the driver arrangement is configured, at a clock level, to drive the first stage circuit in one of the two modes of operation to access the first non-volatile memory cell and, at the clock level, to drive the second stage circuit in the other of the two modes of operation to access the second non-volatile memory cell.

Abstract: According to various embodiments, a write control circuit configured to control writing to a memory cell by applying a writing current to the memory cell may be provided. The write control circuit may include: a current application circuit configured to apply the writing current to the memory cell; a determination circuit configured to determine whether writing to the memory cell is finished; and a stop writing circuit configured to cut off the writing current from the memory cell if it is determined that writing to the memory cell is finished.

Abstract: According to various embodiments, a write control circuit configured to control writing to a memory cell by applying a writing current to the memory cell may be provided. The write control circuit may include: a current application circuit configured to apply the writing current to the memory cell; a determination circuit configured to determine whether writing to the memory cell is finished; and a stop writing circuit configured to cut off the writing current from the memory cell if it is determined that writing to the memory cell is finished.

Abstract: A latch circuit is described comprising a switchable resistive element and a switching circuit configured to set the switchable resistive element to a first resistive state in response to receiving a set signal and to set the switchable resistive element to a second resistive state in response to receiving a reset signal.