Abstract: A system and a method for transcoding multiple media channels is disclosed herein. The system includes a first processor to parse a media data stream having one or more media data channels and a vector processor to decompress, scale, and then compress the parsed media channel. A parsed media data channel, in one embodiment, is accessed using a bit manipulator and packetized into decoder instruction packets and transmitted to the vector processor using a sequencer. The vector processor decompresses the decoder instruction packets, scales a macroblock generated from the packets, and then compresses the scaled macroblock. As a result, the scaled and compressed output has less data associated with the media channel, allowing for faster and/or more efficient storage or transmission. A reduced sized scale buffer is associated with another disclosed embodiment.

Abstract: A method and apparatus for adjusting the amplitude and DC bias of a video signal is presented, which may be performed in preparation for analog-to-digital conversion. This is accomplished by first converting a received voltage mode video signal to a current mode video signal. Similarly, a voltage mode bias control signal is converted to a current mode bias control signal. The amplitude of the current mode video signal is then adjusted to produce an amplitude adjusted video signal. Similarly, the amplitude of the current mode bias signal is adjusted to produce an amplitude adjusted bias control signal. The current mode amplitude adjusted signals are then combined to produce a biased adjusted current mode video signal. The biased adjusted current mode video signal is then converted back to a voltage mode signal, which may be provided to an analog-to-digital converter for conversion.

Abstract: In one embodiment of the present invention, a 10-bit encoded video word is received and stored as two five-bit representations. One of the stored five-bit representations is selected by a multiplexor and provided to a parallel-to-serial converter. The parallel-to-serial converter receives control signals from a multiphase clock. Specifically, the multiphase clock provides a five-phase multi-phased clocks in order to control the parallel-to-serial converter. The serial-to-parallel converter provides a 10-bit serial representation of the 10-bit encoded input.

Abstract: A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, selects data for transfer with the memory over a first bus at a first rate. The multichannel serializer is coupled between the multiplexer and a plurality of controllers through a plurality of second buses. Each of the second buses is associated with a different channel. The multichannel serializer has a serializer for each of the plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate associated with a corresponding controller.

Abstract: A multistage A/D converter and conversion method includes generating a partial A/D bit result of a complete A/D result at a first bit/clock rate based on the received analog input signal and generating remaining A/D bits of the complete A/D result from the partial A/D bit result, at a second and slower bit/clock rate. Accordingly, the partial A/D result output from the first stage is used as input to determine remaining A/D bits to generate a complete A/D result.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: A sample rate conversion system and method uses a digital signal processor (DSP) and a separate sample rate conversion circuit (SRC) to perform multiple stream conversion and mixing of different rate input audio streams. The sample rate conversion system converts data, such as multiple streams of digital audio data sampled at different rates, and performs interpolation, decimation, FIR filtering, and mixing of multiple streams of data using the separate SRC. The SRC uses two bidirectional I/O memories for alternately storing input and output data as part of a sample rate converter. When the sample rate converter writes output to one of the bidirectional memories, it has the option of summing the data with the data already stored in the same I/O memory. Therefore a separate digital signal processor can use the sample rate converter circuit to perform some of the mixing for the multiple streams.

Abstract: A voltage controlled oscillator comprising: a ring of inverters comprised of an odd number of serially connected CMOS inverter stages, the inverter stages being connected between first and second oppositely poled power leads, a MOSFET having a source-drain circuit connected between one of the power leads and a first power rail, the other power lead being connected to a second power rail, apparatus for operating the MOSFET in saturation, and apparatus for applying a control voltage to the gate of the MOSFET, referenced to the second power lead, whereby the MOSFET operates as a nonlinear current conduction device having a characteristic such as to linearize the voltage-frequency characteristic of the combined MOSFET--ring oscillator combination.

Abstract: A charge pump comprising a first branch PMOS FET having a source connected to a voltage source and a drain connected to an output node, a second branch NMOS FET having a drain connected to the output node and a source connected to a ground node, first apparatus for selectively switching a gate of the PMOS FET between its source and a first bias voltage source, and second apparatus for selectively switching a gate of the NMOS FET between its source and a second bias voltage source, the bias voltages being of magnitudes such that the first branch PMOS FET and second branch NMOS FET will source and sink the same magnitude of current when the FETs are fully conducting.

Abstract: A programmable frequency synthesizer comprised of a phase locked loop (PLL) including a current controlled oscillator (ICO), a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate, a reference source of signals, a phase-frequency detector for receiving signals from the reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and apparatus for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied.