Patents by Inventor Hugh J. Griffin
Hugh J. Griffin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220236214Abstract: An atomic level deposition for mass functionalization of a cavity filled with a pathogen sensitive antibody reagent to functionalize each biosensor using atomic level vapor phase deposition enables high volume production of this sensor technology. A biosensor has a first substrate and a second substrate with a cavity formed in the first substrate to form a membrane. Holes are formed through the second substrate. An aluminum oxide layer is formed over the cavity and into the holes to form cores. The cavity is filled with a pathogen sensitive antibody reagent. A biofluid sample with the pathogen is deposited over the membrane. The biofluid is drawn through the cores to mix with the antibody reagent. The antibodies combine with the pathogen to change the impedance along the current path. The presence of the pathogen changes the ionic current flow through the biosensor for a positive detection of the pathogen.Type: ApplicationFiled: February 9, 2021Publication date: July 28, 2022Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Hugh J. Griffin
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Publication number: 20220236261Abstract: An atomic level deposition for mass functionalization of a cavity filled with a pathogen sensitive antibody reagent to functionalize each Biosensor using atomic level vapor phase deposition enables high volume production of this sensor technology. A biosensor has a first substrate and a second substrate with a cavity formed in the first substrate to form a membrane. Holes is formed through the second substrate. An aluminum oxide layer is formed over the cavity and into the holes to form cores. The cavity is filled with a pathogen sensitive antibody reagent. A biofluid sample with the pathogen is deposited over the membrane. The biofluid is drawn through the cores to mix with the antibody reagent. The antibodies combine with the pathogen to change the impedance along the current path. The presence of the pathogen changes the ionic current flow through the biosensor for a positive detection of the pathogen.Type: ApplicationFiled: January 26, 2021Publication date: July 28, 2022Applicant: IceMos Technology LimitedInventors: Samuel J. Anderson, Hugh J. Griffin
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Patent number: 9576842Abstract: A method of manufacturing a semiconductor device includes providing a first semiconductor substrate having a first main surface and an opposing second main surface, and forming a pattern into the first semiconductor substrate. The pattern includes a plurality of trenches defining a plurality of mesas. Each of the plurality of mesas has sidewalls and a free surface formed by material of the first semiconductor substrate. The method further includes forming a cavity in the first semiconductor substrate such that the pattern is recessed in the cavity, forming an oxide layer in the cavity and on the sidewalls and free surfaces of the plurality of mesas, and etching the oxide layer to remove the oxide layer from the free surfaces of the plurality of mesas and at least a portion of the sidewalls of the plurality of mesas.Type: GrantFiled: December 10, 2013Date of Patent: February 21, 2017Assignee: Icemos Technology, Ltd.Inventor: Hugh J. Griffin
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Patent number: 9543380Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.Type: GrantFiled: June 27, 2011Date of Patent: January 10, 2017Inventors: Takeshi Ishiguro, Kenji Sugiura, Hugh J. Griffin
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Publication number: 20160225638Abstract: A method of manufacturing a semiconductor device includes providing a first semiconductor substrate having a first main surface and an opposing second main surface, and forming a pattern into the first semiconductor substrate. The pattern includes a plurality of trenches defining a plurality of mesas. Each of the plurality of mesas has sidewalls and a free surface formed by material of the first semiconductor substrate. The method further includes forming a cavity in the first semiconductor substrate such that the pattern is recessed in the cavity, forming an oxide layer in the cavity and on the sidewalls and free surfaces of the plurality of mesas, and etching the oxide layer to remove the oxide layer from the free surfaces of the plurality of mesas and at least a portion of the sidewalls of the plurality of mesas.Type: ApplicationFiled: December 10, 2013Publication date: August 4, 2016Applicant: ICEMOS TECHNOLOGY LTD.Inventor: Hugh J. GRIFFIN
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Patent number: 8169057Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.Type: GrantFiled: May 7, 2008Date of Patent: May 1, 2012Assignee: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
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Patent number: 8148203Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.Type: GrantFiled: July 8, 2011Date of Patent: April 3, 2012Assignee: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
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Patent number: 8114751Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.Type: GrantFiled: October 28, 2010Date of Patent: February 14, 2012Assignee: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Hugh J. Griffin, Kenji Sugiura
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Patent number: 8058091Abstract: A photodetector includes a semiconductor substrate having first and second main surfaces opposite to each other. The photodetector includes at least one trench formed in the first main surface and a first anode/cathode region having a first conductivity formed proximate the first main surface and sidewalls of the at least one trench. The photodetector includes a second anode/cathode region proximate the second main surface. The second anode/cathode region has a second conductivity opposite the first conductivity. The at least one trench extends to the second main surface of the semiconductor substrate.Type: GrantFiled: July 18, 2008Date of Patent: November 15, 2011Assignee: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
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Publication number: 20110266659Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Applicant: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
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Publication number: 20110254137Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Inventors: Takeshi Ishiguro, Kenji Sugiura, Hugh J. Griffin
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Patent number: 8012806Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.Type: GrantFiled: February 15, 2008Date of Patent: September 6, 2011Assignee: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Kenji Sugiura, Hugh J. Griffin
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Patent number: 7999348Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.Type: GrantFiled: September 4, 2008Date of Patent: August 16, 2011Assignee: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
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Patent number: 7972934Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.Type: GrantFiled: June 19, 2008Date of Patent: July 5, 2011Assignee: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
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Publication number: 20110068440Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.Type: ApplicationFiled: October 28, 2010Publication date: March 24, 2011Applicant: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Hugh J. Griffin, Kenji Sugiura
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Patent number: 7910479Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.Type: GrantFiled: March 26, 2009Date of Patent: March 22, 2011Assignee: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
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Patent number: 7846821Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.Type: GrantFiled: February 13, 2009Date of Patent: December 7, 2010Assignee: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Hugh J. Griffin, Kenji Sugiura
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Patent number: 7821089Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.Type: GrantFiled: September 4, 2008Date of Patent: October 26, 2010Assignee: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
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Patent number: 7795045Abstract: A method of manufacturing a semiconductor wafer having at least one device trench extending to a first depth position includes providing a semiconductor substrate having first and second main surfaces and a semiconductor material layer having first and second main surfaces disposed on the first main surface of the semiconductor substrate and determining an etch ratio. The least one device trench and at least one monitor trench are simultaneously formed in the first main surface of the semiconductor material layer. The at least one monitor trench is monitored to detect when it extends to a second depth position. A ratio of the first depth position to the second depth position is generally equal to the etch ratio.Type: GrantFiled: February 13, 2009Date of Patent: September 14, 2010Assignee: Icemos Technology Ltd.Inventors: Hugh J. Griffin, Takeshi Ishiguro, Kenji Sugiura
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Patent number: 7768085Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.Type: GrantFiled: October 11, 2006Date of Patent: August 3, 2010Assignee: Icemos Technology Ltd.Inventors: Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara