Abstract: A switch for digital communication networks includes a queuing system capable of implementing a broad class of scheduling algorithms for many different applications and purposes, with the queueing system including means for providing numerical tags to incoming cells or packets, the values of the tags being calculated when incoming cells or packets arrive at the switch. A queue and search module is provided to select cells or packets for transmission based on these tags. The combination of the tags and the queue and search module enables simple and fast implementations of a wide variety of scheduling algorithms, including algorithms for supporting communication traffic with real time requirements, continuous media such as audio and video, and traffic requiring very fast response. Furthermore, multiple classes of traffic are supported in a single network switch, each class having its own scheduling algorithm and policy.

Abstract: A computer system having a plurality of processors sharing common memory and data bus structures and operable to perform atomic operations which comprise several instruction actions, wherein the processor performing the atomic operation prevents memory access interruptions by other processors by locking out other processors during the atomic operation. The system bus includes signal paths accommodating bus lock request and bus lock signals which are provided and received by each processor, which signals are initiated by specific bus lock and lock release instructions added to each processor instruction set.