Patents by Inventor Hugh McAdams
Hugh McAdams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140247641Abstract: A method of reducing leakage current in a memory circuit is disclosed (FIG. 8A). The method includes connecting a first supply voltage terminal (VDD) to a bulk terminal of a transistor in an active mode of operation. The method further includes detecting a low power mode (SLEEP) of operation of the transistor and disconnecting the first supply voltage terminal from the bulk terminal in response to the step of detecting.Type: ApplicationFiled: October 11, 2013Publication date: September 4, 2014Applicant: Texas Instruments IncorporatedInventors: Sudhir Madhan, Hugh McAdams
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Publication number: 20140247642Abstract: A memory circuit to reduce active power is disclosed (FIG. 7). The circuit includes a sense amplifier (600). A first bit line (BL) is coupled to a memory array. A second bit line (BLB) that is a complementary bit line to the first bit line is also coupled to the memory array. A first transistor (TG) is coupled between the first bit line (BL) and the sense amplifier. A second transistor (TG) is coupled between the second bit line (BLB) and the sense amplifier. A first drive circuit (700) is coupled between the sense amplifier and the first bit line and is operable to drive a first data signal from the sense amplifier onto the first bit line when the second transistor is off.Type: ApplicationFiled: October 25, 2013Publication date: September 4, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sudhir Madhan, Hugh McAdams
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Patent number: 8811057Abstract: A method of reducing leakage current in a memory circuit is disclosed (FIG. 8A). The method includes connecting a first supply voltage terminal (VDD) to a bulk terminal of a transistor in an active mode of operation. The method further includes detecting a low power mode (SLEEP) of operation of the transistor and disconnecting the first supply voltage terminal from the bulk terminal in response to the step of detecting.Type: GrantFiled: October 11, 2013Date of Patent: August 19, 2014Assignee: Texas Instruments IncorporatedInventors: Sudhir Madan, Hugh McAdams
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Patent number: 8724367Abstract: An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.Type: GrantFiled: September 23, 2011Date of Patent: May 13, 2014Assignee: Texas Instruments IncorporatedInventors: Michael Patrick Clinton, Steven Craig Bartling, Scott Summerfelt, Hugh McAdams
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Patent number: 8717800Abstract: An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).Type: GrantFiled: September 23, 2011Date of Patent: May 6, 2014Assignee: Texas Instruments IncorporatedInventors: Michael Patrick Clinton, Steven Craig Bartling, Scott Summerfelt, Hugh McAdams
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Patent number: 8508974Abstract: A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.Type: GrantFiled: September 22, 2011Date of Patent: August 13, 2013Assignee: Texas Instruments IncorporatedInventors: Michael Patrick Clinton, Steven Craig Bartling, Scott Summerfelt, Hugh McAdams
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Patent number: 8477522Abstract: A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.Type: GrantFiled: September 22, 2011Date of Patent: July 2, 2013Assignee: Texas Instruments IncorporatedInventors: Michael Patrick Clinton, Steven Craig Bartling, Scott Summerfelt, Hugh McAdams
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Publication number: 20120170349Abstract: A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle.Type: ApplicationFiled: September 22, 2011Publication date: July 5, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Patrick Clinton, Steven Craig Bartling, Scott Summerfelt, Hugh McAdams
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Publication number: 20120170350Abstract: An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.Type: ApplicationFiled: September 23, 2011Publication date: July 5, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Patrick Clinton, Steven Craig Bartling, Scott Summerfelt, Hugh McAdams
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Publication number: 20120170348Abstract: A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.Type: ApplicationFiled: September 22, 2011Publication date: July 5, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Patrick Clinton, Steven Craig Bartling, Scott Summerfelt, Hugh McAdams
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Publication number: 20120170351Abstract: An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage).Type: ApplicationFiled: September 23, 2011Publication date: July 5, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Patrick Clinton, Steven Craig Bartling, Scott Summerfelt, Hugh McAdams
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Patent number: 8154938Abstract: An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory.Type: GrantFiled: February 23, 2010Date of Patent: April 10, 2012Assignee: Texas Instruments IncorporatedInventors: Sudhir K. Madan, Hugh McAdams
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Publication number: 20100226162Abstract: An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory.Type: ApplicationFiled: February 23, 2010Publication date: September 9, 2010Applicant: Texas Instruments IncorporatedInventors: Sudhir K. Madan, Hugh McAdams
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Publication number: 20070177422Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open.Type: ApplicationFiled: January 27, 2006Publication date: August 2, 2007Inventor: Hugh McAdams
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Publication number: 20070038805Abstract: A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.Type: ApplicationFiled: August 9, 2005Publication date: February 15, 2007Inventors: Jarrod Eliason, Sudhir Madan, Sung-Wei Lin, Hugh McAdams
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Patent number: 7079408Abstract: A memory circuit and method for reducing gate oxide stress is disclosed. A first data word is stored at a first address in a nonvolatile memory circuit 604. The first address 820 and the first data word 842 are stored in a volatile memory circuit 602. A first external address 608 is applied to the volatile memory circuit. The first external address is compared to the first address. The first data word is produced from the volatile memory circuit on a data bus 610 when the first external address matches the first address. The first data word is produced from the nonvolatile memory circuit on the data bus when the first external address does not match the first address.Type: GrantFiled: August 19, 2003Date of Patent: July 18, 2006Assignee: Texas Instruments IncorporatedInventor: Hugh McAdams
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Publication number: 20050254282Abstract: Methods (200) and systems (108) are provided for reading data from ferroelectric memory cells (106) in which charge is removed from a sense amp input (SABL/SABLB) prior to application of a plateline signal (PL) to the target cell capacitor (CFE). Where the sense amp input (SABL/SABLB) is initially precharged to zero volts, the extraction of charge provides a negative voltage on the data bitline (BL/BLB) when the plateline signal (PL) is applied, allowing adequate voltage to be applied across the cell capacitor (CFE) together with reduced plateline voltages (PL).Type: ApplicationFiled: May 17, 2004Publication date: November 17, 2005Inventors: Scott Summerfelt, Hugh McAdams
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Publication number: 20050207201Abstract: Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.Type: ApplicationFiled: March 22, 2004Publication date: September 22, 2005Inventors: Sudhir Madan, Sung-Wei Lin, Hugh McAdams, Anand Seshadri, Jarrod Eliason
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Publication number: 20050041452Abstract: A memory circuit and method for reducing gate oxide stress is disclosed. A first data word is stored at a first address in a nonvolatile memory circuit 604. The first address 820 and the first data word 842 are stored in a volatile memory circuit 602. A first external address 608 is applied to the volatile memory circuit. The first external address is compared to the first address. The first data word is produced from the volatile memory circuit on a data bus 610 when the first external address matches the first address. The first data word is produced from the nonvolatile memory circuit on the data bus when the first external address does not match the first address.Type: ApplicationFiled: August 19, 2003Publication date: February 24, 2005Inventor: Hugh McAdams
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Patent number: 6819601Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.Type: GrantFiled: June 5, 2003Date of Patent: November 16, 2004Assignee: Texas Instruments IncorporatedInventors: Jarrod Eliason, Bill Kraus, Hugh McAdams, Scott Summerfelt, Theodore S. Moise