Patents by Inventor Hugh Weber Holbrook

Hugh Weber Holbrook has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230135615
    Abstract: A network device is configured to route an ingress packet based on its L2 header. In some configurations the ingress packet is routed based only on the destination MAC (DMAC) address in the L2 header, which allows the network device to begin routing as soon as the DMAC is received. The DMAC can be used in a table look up operation to identify routing actions for a nexthop. An egress packet is produced from the ingress packet using the routing actions. The egress packet is then sent on an egress port specified in the routing actions.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: David SNOWDON, Andrew John Edward BROWN, Hugh Weber HOLBROOK
  • Patent number: 11588756
    Abstract: Each switch unit in a networking system shares its local state information among other switch units in the networking system, collectively referred to as the shared forwarding state. Each switch unit creates a respective set of output queues that correspond to ports on other switch unites based on the shared forwarding state. A received packet on an ingress switch unit operating in accordance with a first routing protocol instance can be enqueued on an output queue in the ingress switch; the packet is subsequently processed by the egress switch unit, operating in accordance with a second routing protocol instance that corresponds to the output queue.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 21, 2023
    Assignee: Arista Networks, Inc.
    Inventors: Francois Labonte, Kartik Chandran, Eswaran Baskaran, Hugh Weber Holbrook
  • Publication number: 20220150186
    Abstract: Each switch unit in a networking system shares its local state information among other switch units in the networking system, collectively referred to as the shared forwarding state. Each switch unit creates a respective set of output queues that correspond to ports on other switch unites based on the shared forwarding state. A received packet on an ingress switch unit operating in accordance with a first routing protocol instance can be enqueued on an output queue in the ingress switch; the packet is subsequently processed by the egress switch unit, operating in accordance with a second routing protocol instance that corresponds to the output queue.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Inventors: Francois LABONTE, Kartik CHANDRAN, Eswaran BASKARAN, Hugh Weber HOLBROOK
  • Patent number: 11265269
    Abstract: Each switch unit in a networking system shares its local state information among other switch units in the networking system, collectively referred to as the shared forwarding state. Each switch unit creates a respective set of output queues that correspond to ports on other switch unites based on the shared forwarding state. A received packet on an ingress switch unit operating in accordance with a first routing protocol instance can be enqueued on an output queue in the ingress switch; the packet is subsequently processed by the egress switch unit, operating in accordance with a second routing protocol instance that corresponds to the output queue.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 1, 2022
    Assignee: Arista Networks, Inc.
    Inventors: Francois Labonte, Kartik Chandran, Eswaran Baskaran, Hugh Weber Holbrook
  • Publication number: 20210273891
    Abstract: Each switch unit in a networking system shares its local state information among other switch units in the networking system, collectively referred to as the shared forwarding state. Each switch unit creates a respective set of output queues that correspond to ports on other switch unites based on the shared forwarding state. A received packet on an ingress switch unit operating in accordance with a first routing protocol instance can be enqueued on an output queue in the ingress switch; the packet is subsequently processed by the egress switch unit, operating in accordance with a second routing protocol instance that corresponds to the output queue.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 2, 2021
    Inventors: Francois LABONTE, Kartik CHANDRAN, Eswaran BASKARAN, Hugh Weber HOLBROOK
  • Patent number: 7391721
    Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms for maintaining counters, such as in, but not limited to a packet switching system, and updating a secondary counter storage based on values of the counters and entries in an overflow buffer. Multiple counter values are stored in a counter bank. An indication of a particular counter of the multiple counters to update is received. A current value of the particular counter is updated in the counter bank, and if an overflow condition results, then an indication of the particular counter is added to an overflow buffer. Periodically each of the multiple counters are visited and corresponding values are updated in a secondary storage, and each entry is retrieved from the overflow buffer and a corresponding value is updated in the secondary storage.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: June 24, 2008
    Assignee: Cisco Technology, Inc.
    Inventor: Hugh Weber Holbrook
  • Patent number: 7237059
    Abstract: Methods and apparatus are disclosed for performing lookup operations using associative memories, including, but not limited to modifying search keys within an associative memory based on modification mappings, forcing a no-hit condition in response to a highest-priority matching entry including a force no-hit indication, selecting among various sets or banks of associative memory entries in determining a lookup result, and detecting and propagating error conditions. In one implementation, each block retrieves a modification mapping from a local memory and modifies a received search key based on the mapping and received modification data. In one implementation, each of the associative memory entries includes a field for indicating that a successful match on the entry should or should not force a no-hit result. In one implementation, an indication of which associative memory blocks or sets of entries to use in a particular lookup operation is retrieved from a memory.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: June 26, 2007
    Assignee: Cisco Technology, Inc
    Inventors: William N. Eatherton, Jaushin Lee, Bangalore L. Priyadarshan, Priyank Ramesh Warkhede, Fusun Ertemalp, Hugh Weber Holbrook, Dileep Kumar Devireddy, Bhushan Mangesh Kanekar, Venkateshwar Rao Pullela
  • Patent number: 7103708
    Abstract: Methods and apparatus are disclosed for performing lookup operations using associative memories, including, but not limited to modifying search keys within an associative memory based on modification mappings, forcing a no-hit condition in response to a highest-priority matching entry including a force no-hit indication, selecting among various sets or banks of associative memory entries in determining a lookup result, and detecting and propagating error conditions. In one implementation, each block retrieves a modification mapping from a local memory and modifies a received search key based on the mapping and received modification data. In one implementation, each of the associative memory entries includes a field for indicating that a successful match on the entry should or should not force a no-hit result. In one implementation, an indication of which associative memory blocks or sets of entries to use in a particular lookup operation is retrieved from a memory.
    Type: Grant
    Filed: August 10, 2002
    Date of Patent: September 5, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: William N. Eatherton, Jaushin Lee, Bangalore L. Priyadarshan, Priyank Ramesh Warkhede, Fusun Ertemalp, Hugh Weber Holbrook, Dileep Kumar Devireddy, Bhushan Mangesh Kanekar, Venkateshwar Rao Pullela
  • Publication number: 20040030803
    Abstract: Methods and apparatus are disclosed for performing lookup operations using associative memories, including, but not limited to modifying search keys within an associative memory based on modification mappings, forcing a no-hit condition in response to a highest-priority matching entry including a force no-hit indication, selecting among various sets or banks of associative memory entries in determining a lookup result, and detecting and propagating error conditions. In one implementation, each block retrieves a modification mapping from a local memory and modifies a received search key based on the mapping and received modification data. In one implementation, each of the associative memory entries includes a field for indicating that a successful match on the entry should or should not force a no-hit result. In one implementation, an indication of which associative memory blocks or sets of entries to use in a particular lookup operation is retrieved from a memory.
    Type: Application
    Filed: August 10, 2002
    Publication date: February 12, 2004
    Inventors: William N. Eatherton, Jaushin Lee, Bangalore L. Priyadarshan, Priyank Ramesh Warkhede, Fusun Ertemalp, Hugh Weber Holbrook