Abstract: The present invention relates to a method for addressing a flat screen composed of lines and columns, with pixels located at their intersections, characterized in that, at the start of each sampling of the video signal to be displayed on the screen, a voltage (Vr) higher than the working voltage range (V) is applied to the selected pixel for a time tr, then the working voltage is sampled for a time ts.

Abstract: A shift register having several cascaded stages, each stage containing an output at a first node connected to a next stage, a first input connected to an output of a preceding stage, a second input connected to an output of the next stage and a first terminal connected to a first clock signal and a second terminal connected to a second clock signal, the stage containing a first semiconductor device switching the output of the stage between high and low values of the first clock signal, the first semiconductor device being controlled by the potential of a second node, itself connected to the output of the preceding stage across a second semiconductor device controlled by the output of the preceding stage; to a negative potential across a third semiconductor device controlled by the output of the next stage; and to the second terminal connected to the second clock signal across a first capacitance, wherein a second capacitance is mounted between the second node and the output of the next stage.