Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.

Abstract: Semiconductor device includes a circuit substrate, a first semiconductor die and a package lid. The first semiconductor die is disposed on and electrically connected to the circuit substrate. The package lid extends over the first semiconductor die and is bonded to the circuit substrate. the package lid comprises a roof extending, a footing and an island. The roof extends along a first direction and a second direction perpendicular to the first direction. The footing is disposed at a peripheral edge of the roof and protrudes from the roof towards the circuit substrate along a third direction perpendicular to the first direction and the second direction. The island protrudes from the roof towards the circuit substrate, wherein the island is disconnected from the footing along the second direction, and the island is physically connected to the footing along the first direction.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: Semiconductor device includes circuit substrate, first semiconductor die, thermal interface material, package lid. First semiconductor die is disposed on and electrically connected to circuit substrate. Thermal interface material is disposed on first semiconductor die at opposite side of first semiconductor die with respect to circuit substrate. Package lid extends over first semiconductor die and is bonded to the circuit substrate. Package lid includes roof, footing, and island. Roof extends along first direction and second direction perpendicular to first direction. Footing is disposed at peripheral edge of roof and protrudes from roof towards circuit substrate along third direction perpendicular to first direction and second direction. Island protrudes from roof towards circuit substrate and contacts thermal interface material on first semiconductor die. Island is disconnected from footing along second direction.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: Disclosed are semiconductor packages and semiconductor devices. In one embodiment, a semiconductor package includes a package, a first integrated passive device, and a second integrated passive device. The first integrated passive device is disposed below the package. The second integrated passive device is disposed between the package and the first integrated passive device. The first integrated passive device is electrically connected to the package through the second integrated passive device.

Abstract: A disclosed semiconductor device includes a package substrate, a first semiconductor die coupled to the package substrate, a package lid attached to the package substrate and covering the semiconductor die, and a thermal interface material located between a top surface of the semiconductor die and an internal surface of the package lid. The semiconductor device may further include a dam formed on the internal surface of the package lid. The dam may constrain the thermal interface material on one or more sides of the first semiconductor die such that the thermal interface material is located within a predetermined volume between the top surface of the first semiconductor die and the internal surface of the package lid during a reflow operation. The package lid may include a metallic material and the dam may include an epoxy material formed as a single continuous structure or may be formed as several disconnected structures.

Abstract: A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.

Abstract: Semiconductor device includes circuit substrate, first semiconductor die, thermal interface material, package lid. First semiconductor die is disposed on and electrically connected to circuit substrate. Thermal interface material is disposed on first semiconductor die at opposite side of first semiconductor die with respect to circuit substrate. Package lid extends over first semiconductor die and is bonded to the circuit substrate. Package lid includes roof, footing, and island. Roof extends along first direction and second direction perpendicular to first direction. Footing is disposed at peripheral edge of roof and protrudes from roof towards circuit substrate along third direction perpendicular to first direction and second direction. Island protrudes from roof towards circuit substrate and contacts thermal interface material on first semiconductor die. Island is disconnected from footing along second direction.

Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Abstract: The present invention provides an electrode arrangement for an OLED display. The OLED display is controlled by a driving circuit. The electrode arrangement includes a plurality of first electrodes in a first direction and a plurality of second electrodes in a second direction. The first direction and the second direction are orthogonal. Each of the plurality of first electrodes includes a plurality set of concaves and convexes and two adjacent sets of the plurality sets of the convexes and concaves are engaged with each other. An overlap between the first electrode and the second electrode forms a light-emitting region of the OLED display.

Abstract: An organic electroluminescent device for preventing long distance short comprises an isolated separating layer unit provided on an organic light emitting layer and the two sides of an second electrode, and an isolating trench further provided between a first isolated separating layer and a second isolated separating layer of the isolated separating layer unit. Accordingly, the isolating trench is provided for preventing the irregular electrical contact from the first electrical conducting layer of the top of the first isolated separating layer and the second electrical conducting layer of the top of the second isolated separating layer, that is, the irregularly lighting by the pixels can be prevented from the long distance short for the organic electroluminescent device.

Abstract: An organic electroluminescent device with improved lifetime and a method of fabricating the same are provided. The device comprises a barrier layer on an upper surface of a color filter, and etching and removing part of the barrier layer uncovered by first electrodes to form moistness removed channel after defining and forming at least one first electrode on an upper surface of the barrier layer. It is convenient to bake and eliminate a solvent or mist existed in the color filter in a baking process, thereby reducing speed of going bad of the organic light emitting layer and effectively improving lifetime of the organic electroluminescent device.

Abstract: An electrode structure of an organic electroluminescent display panel and a method of manufacturing the same are provided. The electrode structure comprises a transparency substrate, a leading wire pattern layer (for example: ITO, IZO or IWO materials etc.) grown on the transparency substrate, at least one auxiliary metallic pattern layer grown on the leading wire pattern layer, an isolation area provided on the auxiliary metallic pattern layer for isolation, a separation area provided on the isolation area with an raised predetermined height to separate electric interference, and at least one metallic conductive layer provided on the transparency substrate and the separation area.

Abstract: A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CXFYHZ or a fluorocarbon and a gas such as O2, H2, N2, N2O, CO, CO2, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.

Abstract: A method of reducing a charge on a substrate to prevent an arcing incident in a subsequent etch process is described. A patterned substrate is fastened to a chuck in a process chamber. A discharge process is performed that includes the three steps of (a) coupling the chuck to a 0 volt connection, (b) generating a plasma, and (c) coupling the chuck to a high voltage connection. The three steps are carried out in any sequence. An inert gas or an inert gas and an etching gas are flowed into the chamber during the discharge sequence. Alternatively, a fluorocarbon CXFYHZ or a fluorocarbon and a gas such as O2, H2, N2, N2O, CO, CO2, He or Ar is flowed into the chamber during the discharge sequence. The method is compatible with batch or single wafer processes and is extendable to etching low k dielectric layers with poor thermal conductivity.