Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A dynamic command protection method includes generating salt data by a physically linked device after an authentication of the physically linked device is verified, transmitting the salt data from the physically linked device to a computer terminal, transmitting at least one command protected by the salt data during a first time interval from the computer terminal to the physically linked device, verifying the salt data if the at least one command is valid, executing at least one valid command after the salt data is successfully verified, and updating the salt data after the first time interval elapses. The salt data is bound to the physically linked device and is generated according to a time-varying value.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: An exerciser includes an exercising mechanism for being operated by a user who may spend and consume an energy to operate the exercising mechanism, an electric generating device coupled to the exercising mechanism for being actuated by the exercising mechanism to generate an electric energy, a converter coupled to the electric generating device for receiving and converting the electric energy into an alternate current, an electric energy reservoir coupled to the converter for receiving the alternate current generated by the converter, and a control circuit for the exerciser may be coupled to the converter for being energized with the alternate current generated by the converter.

Abstract: A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation. Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel.

Abstract: A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation. Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel.

Abstract: A new method is provided for treating the surface of a layer of passivation where this layer of passivation comprises silicon dioxide or silicon nitride. An oxygen rich layer is created over the surface of the layer of passivation. Under the first embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of plasma enhanced silicon nitride is deposited over the surface of the layer of silicon oxide, and a layer of oxynitride is deposited over the surface of the layer of plasma enhanced silicon nitride. Under the second embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of silicon nitride is deposited over the surface of layer of silicon oxide. The surface of the layer of silicon nitride is oxidized by N2O or O2 plasma treatment.

Abstract: Alternative voltage stabilizer for improving transient response and increasing area of stabilized voltage composed of a low pass input filter circuit, a wave dividing circuit, a voltage reducing and width modulating circuit, a voltage supplementing and width modulating circuit, a wave recombining circuit and a low pass output filter circuit, it divides the supply voltage into positive and negative half cycles, supplements or reduces the waves by on-off transistors, capacitors and inductors therein, and recombines and recovers them to be rated stable voltage outputs, has the advantage of low dynamic output impedance, fast response, good stabilizing ratio and transient response, and broader areas of stabilized voltage, suits the case which activates frequently or severely reqires for stable voltage.