Abstract: A method of coating an edge surface of an optical lens is provided. The method includes providing an optical lens comprising a first optical surface and an opposing second optical surface, wherein the first and the second optical surfaces are connected by an edge surface, disposing at least one temporary protective material on at least a portion of a perimeter portion of one or both of the first and the second optical surfaces abutting the edge surface, disposing at least one coating material on the edge surface of the optical lens to obtain at least one edge coating, and removing any excess coating material disposed on the at least one temporary protective material. An optical lens having at least one temporary protective material disposed on only at least a portion of a perimeter portion of one or both of the first and the second optical surfaces abutting the edge surface is also provided.

Abstract: A transistor structure includes a substrate, a source electrode, a drain electrode, a protective layer and a gate electrode. The source electrode and the drain electrode are provided on the substrate. The protective layer is provided on the substrate. The protective layer is provided between the source electrode and the drain electrode. The protective layer includes a SiNx layer and a SiOx layer. The SiOx layer is provided on the substrate, the SiNx layer is provided on the SiOx layer, and a through hole of the protective layer is formed to extend through the SiNx layer and the SiOx layer. The gate electrode is provided in the through hole, and the gate electrode is separated from at least part of the SiOx layer so as to form an air gap therebetween.

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A first pad layer is formed on a substrate. Isolation structures are formed in the first pad layer and the substrate. At least one shape modification treatment is performed on the isolation structures. Each shape modification treatment includes the following steps. A first etching process is performed on the first pad layer to reduce a height of the first pad layer and to form first openings exposing sidewalls of the isolation structures. After the first etching process is performed, a second etching process is performed on the isolation structures to modify shapes of the sidewalls of the isolation structures exposed by the first openings. The first pad layer is removed to form a second opening between two adjacent isolation structures.

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A first pad layer is formed on a substrate. Isolation structures are formed in the first pad layer and the substrate. At least one shape modification treatment is performed on the isolation structures. Each shape modification treatment includes the following steps. A first etching process is performed on the first pad layer to reduce a height of the first pad layer and to form first openings exposing sidewalls of the isolation structures. After the first etching process is performed, a second etching process is performed on the isolation structures to modify shapes of the sidewalls of the isolation structures exposed by the first openings. The first pad layer is removed to form a second opening between two adjacent isolation structures.

Abstract: Disclosed herein is a multilayered article comprising a core layer comprising a thermoplastic polymer; where the thermoplastic polymer comprises a polyolefin, thermoplastic starch, and a compatibilizer; where the compatibilizer does not contain ethylene acrylic acid; where the polyolefin is not polypropylene and where the polyolefin present in an amount of greater than 40 wt %, based on a total weight of the core layer; a first layer comprising a thermoplastic resin; and a second layer comprising a thermoplastic resin; where the first layer and the second layer are devoid of fillers; where the first layer is disposed on a side of the core layer that is opposed to the side that contacts the second layer; where the multilayered article has an optical clarity of greater than 80% when measured as per ASTM D 1746 and a total haze less than 8% when measured as per ASTM D 1003.

Abstract: The invention provides a manufacturing method of a metal-insulator-metal device, including: forming a first metal layer, an insulation layer, and a second metal layer sequentially on a base to form a metal-insulator-metal structure; forming a patterned mask layer on at least a portion of the second metal layer, etching the second metal layer and the insulation layer on which the patterned mask layer is not formed using an etchant without carbon; and cleaning the etched metal-insulator-metal structure using a mixed solution containing oxidants and metal oxide etchants to remove excess polymer remaining on the metal-insulator-metal structure.

Abstract: Disclosed herein is a multilayered article comprising a core layer comprising a thermoplastic polymer; where the thermoplastic polymer comprises a polyolefin, thermoplastic starch, and a compatibilizer; where the compatibilizer does not contain ethylene acrylic acid; where the polyolefin is not polypropylene and where the polyolefin present in an amount of greater than 40 wt %, based on a total weight of the core layer; a first layer comprising a thermoplastic resin; and a second layer comprising a thermoplastic resin; where the first layer and the second layer are devoid of fillers; where the first layer is disposed on a side of the core layer that is opposed to the side that contacts the second layer; where the multilayered article has an optical clarity of greater than 80% when measured as per ASTM D 1746 and a total haze less than 8% when measured as per ASTM D 1003.

Abstract: Embodiments of the present disclosure provide optical link handshake techniques and configurations. In one embodiment, an optical module includes a laser driver corresponding with a channel of the optical module, a signal detector corresponding with the channel, and a link handshake state machine configured to control the laser driver to generate a connect pulse of a link handshake process to test an optical link between the channel and a corresponding channel of another optical module and monitor the signal detector to detect a connect pulse from the another optical module. Other embodiments may be described and/or claimed.

Abstract: A system includes two optical modules that perform auto-setting of the optical links between the optical modules. One optical module sends an optical signal with a test pattern to the other optical module. If the receiving module determines that the test pattern is successfully received, it sends a pass indication to the transmitting module, and the transmitting module can configure its driver path in accordance with a transmit current setting used to transmit the test pattern. If the test pattern is not successfully received, the receiving module sends a fail indication, and the transmitting module can increase the transmit current setting and resend the test pattern. When the system includes multiple optical channels, one channel can be tested while feedback is provided on another channel. The system can iterate through all optical channels until they are all configured.

Abstract: Embodiments of the present disclosure provide laser safety techniques and configurations. In one embodiment, an optical module includes a first die including a laser configured to transmit optical signals, a first node electrically coupled with the laser, and a second node electrically coupled with the laser, and a second die including a power supply line configured to provide power to the laser, a third node electrically coupled with the power supply line and electrically coupled with the first node to provide the power to the laser, a fourth node electrically coupled with the second node of the first die, and a switch configured to prevent the power of the power supply line from reaching the laser through the third node based on a voltage of the fourth node when a laser fault event occurs. Other embodiments may be described and/or claimed.

Abstract: A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamic reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost.

Abstract: A circuit comprising a first transistor group configured to electrically isolate, at least in part, a second transistor group from an input voltage; the second transistor group configured to provide voltage protection to a third transistor group; and the third transistor group configured to switch on and off.

Abstract: Embodiments of the present disclosure provide laser safety techniques and configurations. In one embodiment, an optical module includes a first die including a laser configured to transmit optical signals, a first node electrically coupled with the laser, and a second node electrically coupled with the laser, and a second die including a power supply line configured to provide power to the laser, a third node electrically coupled with the power supply line and electrically coupled with the first node to provide the power to the laser, a fourth node electrically coupled with the second node of the first die, and a switch configured to prevent the power of the power supply line from reaching the laser through the third node based on a voltage of the fourth node when a laser fault event occurs. Other embodiments may be described and/or claimed.

Abstract: A power management arrangement for low power optical transceiver such as those that may be integrated into a personal computer or server may periodically put itself into a power conservation or sleep mode which assures the transceiver is available upon wake-up.

Abstract: A dynamic reconfigurable heterogeneous processor architecture with load balancing and dynamic allocation method thereof is disclosed. The present invention uses a work control logic unit to detect load imbalance between different types of processors, and employs a number of dynamic reconfigurable heterogeneous processors to offload the heavier loaded processors. Hardware utilization of such design can be enhanced, and variation in computation needs among different computation phases can be better handled. To design the dynamic reconfigurable heterogeneous processors, a method of how to choose the basic building blocks and place the routing components is included. With the present invention, performance can be maximized at a minimal hardware cost. Hence the dynamic reconfigurable heterogeneous processor(s) so constructed and the load balancing and dynamic allocation method together will have the best performance at least cost.