Patents by Inventor Hui-Chuan Lu
Hui-Chuan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811367Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: GrantFiled: March 21, 2019Date of Patent: October 20, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Publication number: 20190287928Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: ApplicationFiled: March 21, 2019Publication date: September 19, 2019Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Patent number: 10340228Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: GrantFiled: September 7, 2017Date of Patent: July 2, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Publication number: 20180068959Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: ApplicationFiled: September 7, 2017Publication date: March 8, 2018Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Patent number: 9786610Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: GrantFiled: August 12, 2015Date of Patent: October 10, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Publication number: 20160141255Abstract: A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom surface; at least a semiconductor element disposed on the first top surface of the circuit structure and electrically connected to the circuit structure; an encapsulant formed on the first top surface of the circuit structure to encapsulate the semiconductor element, wherein the encapsulant has a second bottom surface facing the first top surface of the circuit structure and a second top surface opposite to the second bottom surface; and a strengthening layer formed on the second top surface of the encapsulant, or formed between the circuit structure and the encapsulant, or formed on the first bottom surface of the circuit structure, thereby effectively preventing the encapsulant from warping and the semiconductor element from cracking.Type: ApplicationFiled: August 12, 2015Publication date: May 19, 2016Inventors: Hui-Chuan Lu, Chun-Hung Lu, Po-Yi Wu
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Patent number: 7544581Abstract: A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on a non-active area of the substrate; and staining the marking pattern or filling a material having low transmittance ratio into the marking pattern. The present invention further discloses a method for making a display substrate, including the steps: providing a substrate; forming a shadow layer on a non-active area of the substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on the shadow layer of the non-active area on the substrate; and removing a part of the shadow layer not covered by the marking pattern.Type: GrantFiled: February 29, 2008Date of Patent: June 9, 2009Assignee: Chunghwa Picture Tubes, Ltd.Inventors: De-Jiun Li, Yen-Ju Chen, Yi-Cheng Tsai, Der-Chun Wu, Yui-Chen Liu, Kuo-Ching Chou, Hui-Chuan Lu
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Publication number: 20090011567Abstract: A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on a non-active area of the substrate; and staining the marking pattern or filling a material having low transmittance ratio into the marking pattern. The present invention further discloses a method for making a display substrate, including the steps: providing a substrate; forming a shadow layer on a non-active area of the substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on the shadow layer of the non-active area on the substrate; and removing a part of the shadow layer not covered by the marking pattern.Type: ApplicationFiled: February 29, 2008Publication date: January 8, 2009Applicant: Chunghwa Picture Tubes, Ltd.Inventors: De-Jiun Li, Yen-Ju Chen, Yi-Cheng Tsai, Der-Chun Wu, Yui-Chen Liu, Kuo-Ching Chou, Hui-Chuan Lu
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Publication number: 20070133928Abstract: A canted-fiber duplex optical subassembly is disclosed herein. The optical subassembly transmits and receives optical signals by way of a single optical fiber, which has a canted surface on one end. A light source sends transmission optical signals, which are refracted through the canted surface and then enter the optical fiber. Reception optical signals in the optical fiber are reflected by the canted surface and are then received by an optical detector.Type: ApplicationFiled: March 13, 2006Publication date: June 14, 2007Applicant: Industrial Technology Research InstituteInventors: Chih-Hsiang Ko, Ming-Lang Tsai, Hui-Chuan Lu, Jin-Sheng Chang
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Patent number: 6900136Abstract: A method for reducing RIE lag (reaction ion etching lag) in a deep silicon etching process forming trench openings is described. The method can be carried out by either a photolithographic means wherein trench openings of the same planar area are patterned on the silicon substrate, or by a pressure means in which the chamber pressure during the reactive ion etching process is increased to reduce or eliminate the RIE lag effect. By increasing the chamber pressure at least 50% from that normally incurred in a reactive ion etching process, and preferably at least 100%, the RIE lag effect can be completely eliminated resulting in an inversed RIE lag in which a larger etch depth is achieved for the trench openings that have the smallest width.Type: GrantFiled: March 8, 2002Date of Patent: May 31, 2005Assignee: Industrial Technology Research InstituteInventors: Chen-Kuei Chung, Hui-Chuan Lu
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Publication number: 20030171000Abstract: A method for reducing RIE lag (reaction ion etching lag) in a deep silicon etching process forming trench openings is described. The method can be carried out by either a photolithographic means wherein trench openings of the same planar area are patterned on the silicon substrate, or by a pressure means in which the chamber pressure during the reactive ion etching process is increased to reduce or eliminate the RIE lag effect. By increasing the chamber pressure at least 50% from that normally incurred in a reactive ion etching process, and preferably at least %, the RIE lag effect can be completely eliminated resulting in an inversed RIE lag in which a larger etch depth is achieved for the trench openings that have the smallest width.Type: ApplicationFiled: March 8, 2002Publication date: September 11, 2003Applicant: Industrial Technology Research InstituteInventors: Chen-Kuei Chung, Hui-Chuan Lu