Patents by Inventor Hui-Hua Chang
Hui-Hua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126728Abstract: JSON Duality Views are object views that return JDV objects. JDV objects are virtual because they are not stored in a database as JSON objects. Rather, JDV objects are stored in shredded form across tables and table attributes (e.g. columns) and returned by a DBMS in response to database commands that request a JDV object from a JSON Duality View. Through JSON Duality Views, changes to the state of a JDV object may be specified at the level of a JDV object. JDV objects are updated in a database using optimistic lock.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Inventors: ZHEN HUA LIU, JUAN R. LOAIZA, SUNDEEP ABRAHAM, SHUBHA BOSE, HUI JOE CHANG, SHASHANK GUGNANI, BEDA CHRISTOPH HAMMERSCHMIDT, TIRTHANKAR LAHIRI, YING LU, DOUGLAS JAMES MCMAHON, AUROSISH MISHRA, AJIT MYLAVARAPU, SUKHADA PENDSE, ANANTH RAGHAVAN
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Publication number: 20240126743Abstract: JSON Duality Views are object views that return JDV objects. JDV objects are virtual because they are not stored in a database as JSON objects. Rather, JDV objects are stored in shredded form across tables and table attributes (e.g. columns) and returned by a DBMS in response to database commands that request a JDV object from a JSON Duality View. Through JSON Duality Views, changes to the state of a JDV object may be specified at the level of a JDV object. JDV objects are updated in a database using optimistic lock.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Inventors: ZHEN HUA LIU, JUAN R. LOAIZA, SUNDEEP ABRAHAM, SHUBHA BOSE, HUI JOE CHANG, SHASHANK GUGNANI, BEDA CHRISTOPH HAMMERSCHMIDT, TIRTHANKAR LAHIRI, YING LU, DOUGLAS JAMES MCMAHON, AUROSISH MISHRA, AJIT MYLAVARAPU, SUKHADA PENDSE, ANANTH RAGHAVAN
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Publication number: 20240126816Abstract: Herein is database query acceleration from dynamic discovery of whether contents of a persistent column can be stored in an accelerated representation in storage-side memory. In an embodiment, based on data type discovery, a storage server detects that column values in a persistent column have a particular data type. Based on storage-side metadata including a frequency of access of the persistent column as an offload input column for offload computation requests on a certain range of memory addresses, the storage server autonomously decides to generate and store, in storage-side memory in the storage server, an accelerated representation of the persistent column that is based on the particular data type. The storage server receives a request to perform an offload computation for the offload input column. Based on the accelerated representation of the persistent column, execution of the offload computation is accelerated.Type: ApplicationFiled: September 29, 2023Publication date: April 18, 2024Inventors: Jorge Luis Issa Garcia, Teck Hua Lee, Sheldon Andre Kevin Lewis, Bangalore Prashanth, Hui Joe Chang, Zhen Hua Liu, Aurosish Mishra, Shasank K. Chavan
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Publication number: 20240126729Abstract: JSON Duality Views are object views that return JDV objects. JDV objects are virtual because they are not stored in a database as JSON objects. Rather, JDV objects are stored in shredded form across tables and table attributes (e.g. columns) and returned by a DBMS in response to database commands that request a JDV object from a JSON Duality View. Through JSON Duality Views, changes to the state of a JDV object may be specified at the level of a JDV object. JDV objects are updated in a database using optimistic lock.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Inventors: ZHEN HUA LIU, JUAN R. LOAIZA, SUNDEEP ABRAHAM, SHUBHA BOSE, HUI JOE CHANG, SHASHANK GUGNANI, BEDA CHRISTOPH HAMMERSCHMIDT, TIRTHANKAR LAHIRI, YING LU, DOUGLAS JAMES MCMAHON, AUROSISH MISHRA, AJIT MYLAVARAPU, SUKHADA PENDSE, ANANTH RAGHAVAN
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Patent number: 11961811Abstract: A semiconductor structure includes a semiconductor element and a first bonding structure. The semiconductor element has a first surface and a second surface opposite to the first surface. The first bonding structure is disposed adjacent to the first surface of the semiconductor element, and includes a first electrical connector, a first insulation layer surrounding the first electrical connector and a first conductive layer surrounding the first insulation layer.Type: GrantFiled: June 14, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Jui Kuo, Hui-Jung Tsai, Tsao-Lun Chang
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Publication number: 20240099154Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: UNITED MICROELECTRONICS CORPInventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
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Patent number: 11917923Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
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Publication number: 20120019461Abstract: The present invention provides a touch display device, which includes a display module and a touch panel. The display module includes a display panel and a control chip disposed on the display module to control the display module. The touch panel has a glass substrate and a driving chip disposed on the glass substrate to control at least one touching operation for the touch panel. The driving chip and the control chip are disposed in a misaligned manner.Type: ApplicationFiled: May 19, 2011Publication date: January 26, 2012Applicant: CHIMEI INNOLUX CORPORATIONInventors: Hui-Hua CHANG, Yu-Chun TSENG, Shu-Hui HSIAO
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Patent number: 6419984Abstract: Several modifications have been made to the LPCVD equipment of the prior art in order to reduce the amount of particulate contamination. A bypass vent has been added in parallel with the main vacuum exhaust gate valve. Said bypass vent is left open during loading and unloading of the system with wafers that are to be processed, thereby ensuring a steady flow of air away from them at all times. Additionally, the section of the vacuum line immediately adjacent to the reaction chamber is heated. An example of the application of said modified equipment to LPCVD is provided as well as test results that illustrate the efficacy of the new equipment and method.Type: GrantFiled: August 7, 1995Date of Patent: July 16, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Hui-Hua Chang
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Patent number: 5950094Abstract: The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions.Type: GrantFiled: February 18, 1999Date of Patent: September 7, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chi Lin, Hui-ju Yu, Yen-Ming Chen, Hui-Hua Chang
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Patent number: 5838716Abstract: A method of testing a dry oxidation furnace for leaks which permit the entry of moisture into the oxidizing ambient is described. Such moisture, when present in sufficient concentration, can cause a high degree of boron depletion in silicon at p-type contact interfaces in the manufacture of p-channel MOSFETs. The depleted silicon presents a high resistance component to the contact thereby compromising its performance. A test wafer is subjected to a non-oxidizing ambient in the furnace according to a prescribed procedure. Measurements of the thickness of an oxide layer on the test wafer before and after the procedure indicate the presence of a leak of sufficient proportions to cause a deterioation of contact performance if the oxide grown during the test procedure exceeds between about 25 to 35 Angstroms. The procedure is also useful as a simple means of monitoring an oxidation furnace to provide a record of performance and signal the development of trends which suggest appropriate remedial maintenance.Type: GrantFiled: June 3, 1997Date of Patent: November 17, 1998Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Hua Chang, Yu-Jen Yu, Chi-Fu Ni