Abstract: Techniques are generally described related to a multi-channel storage system. One example multi-channel storage system may include a plurality of memory-controllers, each memory-controller configured to control one or more storage units. The multi-channel storage system may further include a multi-channel interface having a plurality of input-output (IO) channels; and a channel-controller switch configured to support data communications between any one of the plurality of IO channels and any one of the plurality of memory-controllers. Upon receiving a request instructing using at least two of the plurality of IO channels and at least two of the plurality of memory-controllers, the multi-channel interface of the multi-channel storage system is configured to utilize the channel-controller switch to concurrently transfer data via the at least two of the plurality of IO channels or the at least two of the plurality of memory-controllers.

Abstract: Techniques generally described are related to a flexible storage block based on solid state devices. One example method to update data stored in a storage block may include maintaining, by a flash storage module, a cluster link in the storage block for storing a file, wherein the cluster link links together a plurality of data clusters that are storage spaces provided by one or more solid state devices. The method may include, in response to a first request to update data stored in a first data cluster amongst the plurality of data clusters, allocating a second data cluster to store the updated data. The method may further include linking the second data cluster to the cluster link, wherein the linking the second data cluster to the cluster link invalidates the first data cluster in the cluster link.

Abstract: Technologies are generally described for a multi-layer file system. In the multi-layer file system, a file is arranged into two or more data blocks respectively associated with corresponding multi-entry file indices. Each multi-entry file index can point to a location index at the beginning of a linked list (an initial entry in the linked list). The linked list may have at least one location index as an entry to identify a location in the storage device where the associated data block is stored.

Abstract: One example scalable storage system may include a first storage channel including a first storage node and a second storage node. The first storage node is coupled with the second storage node via a serial link. The scalable storage system may include a multi-channel interface including an input-channel coupled with the first storage node and an output-channel coupled with the second storage node. After receiving a request, the multi-channel interface may direct the request via the input-channel to the first storage node of the first storage channel. The first storage node may process the request. If a request segment in the request is directed to the second storage node, the serial link may transmit the request segment from the first storage node to the second storage node, allowing the second storage node to process the request segment.

Abstract: Techniques generally described are related to a flexible storage block based on solid state devices. One example method to update data stored in a storage block may include maintaining, by a flash storage module, a cluster link in the storage block for storing a file, wherein the cluster link links together a plurality of data clusters that are storage spaces provided by one or more solid state devices. The method may include, in response to a first request to update data stored in a first data cluster amongst the plurality of data clusters, allocating a second data cluster to store the updated data. The method may further include linking the second data cluster to the cluster link, wherein the linking the second data cluster to the cluster link invalidates the first data cluster in the cluster link.

Abstract: Embodiments of the disclosure set forth energy storage devices. Some example energy storage devices include a first hybrid capacitor, a first battery and an electric double-layer capacitor. The first hybrid capacitor includes a first positive electrode, a first negative electrode and a first electrolyte. The first battery couples to the first hybrid capacitor and includes a second positive electrode, a second negative electrode and a second electrolyte. The electric double-layer capacitor couples to the first battery and includes a third positive electrode, a third negative electrode and a third electrolyte. The first positive electrode includes the second positive electrode.

Abstract: Technologies are generally described for a multi-layer file system. In the multi-layer file system, a file is arranged into two or more data blocks respectively associated with corresponding multi-entry file indices. Each multi-entry file index can point to a location index at the beginning of a linked list (an initial entry in the linked list). The linked list may have at least one location index as an entry to identify a location in the storage device where the associated data block is stored.

Abstract: A scaling device for receiving and scaling a digital image signal includes a scaling module and a data quantity control logic. The scaling module scales the digital image signal and then outputs a scaled output signal according to a scaling ratio. The data quantity control logic controls output quantity of the scaled output signal according to a scaling ratio. Thus, when the data quantity outputted from the scaling module is controlled within the data quantity that may be processed by the post stage of the scaling module per unit time, the data quantities that may be processed per unit time in the post stage processing devices of the scaling module approximate a constant value such that the post stage processing speed of the scaling module may be increased.

Abstract: Techniques are generally described related to a scalable storage system. One example scalable storage system may include a first storage channel including a first storage node, a second storage node, and a first serial link. The first storage node is coupled with the second storage node via the first serial link. The scalable storage system may include a multi-channel interface including a first input-channel coupled with the first storage node and a first output-channel coupled with the second storage node. For a first request transmitted from a computer system and received by the multi-channel interface, the multi-channel interface is configured to direct the first request via the first input-channel to the first storage node of the first storage channel. The first storage node is configured to process the first request.

Abstract: Techniques are generally described related to a multi-channel storage system. One example multi-channel storage system may include a plurality of memory-controllers, each memory-controller configured to control one or more storage units. The multi-channel storage system may further include a multi-channel interface having a plurality of input-output (IO) channels; and a channel-controller switch configured to support data communications between any one of the plurality of IO channels and any one of the plurality of memory-controllers. Upon receiving a request instructing using at least two of the plurality of IO channels and at least two of the plurality of memory-controllers, the multi-channel interface of the multi-channel storage system is configured to utilize the channel-controller switch to concurrently transfer data via the at least two of the plurality of IO channels or the at least two of the plurality of memory-controllers.

Abstract: An electroluminescent tube compatible with a conventional fluorescent lighting system is generally described in the present disclosure. One example electroluminescent tube may include a rectifying circuit, a driving circuit, and an electroluminescent device. The driving circuit is configured to drive the electroluminescent device upon receiving a power signal. The rectifying circuit is configured to bypass a starter route and also direct the power signal to the driving circuit through a power input route.

Abstract: An electroluminescent tube compatible with a conventional fluorescent lighting system is generally described in the present disclosure. One example electroluminescent tube may include a rectifying circuit, a driving circuit, and an electroluminescent device. The driving circuit is configured to drive the electroluminescent device upon receiving a power signal. The rectifying circuit is configured to bypass a starter route and also direct the power signal to the driving circuit through a power input route.

Abstract: An error correction device includes a main memory, a memory bus coupled to the main memory, and a correction module. The correction module is coupled to the system bus and directly connected to the memory bus. The correction module reads an error data from the main memory via the memory bus according to an error address, generates a correct data according to the error data and an error value, and directly writes the correct data into the main memory via the memory bus. Because the correction module reads and writes the correct data into the main memory without using the system bus managed by an arbitrator, a number of the change row operations can be reduced to increase system efficiency.

Abstract: An error correction device includes a decoding unit, an error buffer, an error classifying unit and an error correction unit. The decoding unit reads data from a main memory and performs error detection on the data to generate error values and error addresses. Then, the error buffer temporarily stores the error values and the error addresses. The error classifying unit classifies the error addresses stored in the error buffer into a plurality of subclasses, where error values and error addresses which correspond to the same row of the main memory are classified into the same subclass. Finally, the error correction unit performs an error correction on the data stored in the main memory according to the plurality of subclasses. The error correction device therefore can reduce the amount of the change-row operations of the main memory so that the memory efficiency is increased.

Abstract: A decoding device is used to deal with an uncorrected data stored in a data storage device, the uncorrected data containing a inner-code parity (PI) direction error data and a outer-code parity (PO) direction error data, the decoding device including: an error correction unit receiving the uncorrected data and correcting the PO direction error data of the uncorrected data according to a PO direction decoding and correcting information, and then outputting a data; a data buffer for buffering the data, after correcting the PI direction error data of the data, then outputting a corrected data; a PI decoding unit for decoding and correcting the PI error direction error data of the data stored in the data buffer; and a PO decoding unit for generating the PO direction decoding and correcting information to the error correction unit according to the data stored in the data buffer.

Abstract: A memory management apparatus and a related method thereof for accessing digital versatile disc(DVD) data stored in a memory device are disclosed. The memory management apparatus includes an address mapping module, coupled to a bus, for receiving a logic address from the bus and for generating a physical address according to the logic address, and an access control module, coupled to the address mapping module and the memory device, for accessing the digital versatile disc data according to the physical address.

Abstract: The present invention provides a controlling apparatus and method for an image scanning system that includes a direct current (DC) motor and an image sensor driven by the DC motor to move. A position signal representative of the position associated of the image sensor is generated and the controlling apparatus and method is performed according to the position signal.

Abstract: This invention is related to a method and an apparatus for reducing the zippers of image. The method uses a recovery model to reduce the zippers of image. The recovered model performs calculations which comprise the steps of setting a type of light sources and a sensing mode, measuring a voltage difference, estimating an amount of interference by a statistic method and establishing an interference model according to the amount of interference, and calculating the recovered model according to the interference model.

Abstract: A chip design-in aid system, wherein the chip has a plurality of chip controlling registers for storing at least one parameter. The system includes a user interfance for inputting user setting data, the user setting data corresponding to at least one function of the chip; a data processing unit for processing the user setting data; and a parameter adjusting unit for receiving the processed user setting data from the data processing unit, and transmitting the processed user setting data to the chip, so as to adjust the parameter stored in the chip controlling registers, whereby the chip is set to perform the function corresponding to the user setting data.

Abstract: An error diffusion method applied to halftone processing for image data. The image data comprise a plurality of pixels. The method comprising the steps of dividing the image data into a plurality of image blocks; selecting one of the pixels belonging to each of the image blocks as a target pixel, wherein the target pixel is located on the boundary of the corresponding image block; assigning a predicted error to the target pixel; and executing the error diffusion method on the rest of the pixels of the image blocks according to the predicted error of the target pixels of the image blocks. When the error diffusion is performed, target pixels are found in the image block and then predicted errors are assigned to the target pixels in order to calculate their output values. The target pixels are located at boundaries of the image blocks, and the predicted errors may be 0 or the transversal or longitudinal errors outputted from the pixels above the target pixels.