Patents by Inventor Hui-Min Lin
Hui-Min Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990440Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.Type: GrantFiled: August 27, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chang-Jung Hsueh, Kai-Jun Zhan, Yung-Sheng Lin
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Publication number: 20240163947Abstract: A method for multi-link operation (MLO) is provided. The method for MLO may be applied to an apparatus. The method for MLO may include the following steps. A multi-chip controller of the apparatus may assign different data to a plurality of chips of the apparatus, wherein each chip corresponds to one link of multi-links. Each chip may determine whether transmission of the assigned data has failed. A first chip of the chips may transmit the assigned data to an access point (AP) in response to the first chip determining that the transmission of the assigned data has not failed.Type: ApplicationFiled: November 8, 2023Publication date: May 16, 2024Inventors: Cheng-Ying WU, Wei-Wen LIN, Shu-Min CHENG, Hui-Ping TSENG, Chi-Han HUANG, Chih-Chun KUO, Yang-Hung PENG, Hao-Hua KANG
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Publication number: 20240153896Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 11978678Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.Type: GrantFiled: August 5, 2022Date of Patent: May 7, 2024Assignee: INNOLUX CORPORATIONInventors: Tung-Kai Liu, Tsau-Hua Hsieh, Wei-Cheng Chu, Chun-Hsien Lin, Chandra Lius, Ting-Kai Hung, Kuan-Feng Lee, Ming-Chang Lin, Tzu-Min Yan, Hui-Chieh Wang
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Publication number: 20240128148Abstract: A method includes attaching a package component to a package substrate, the package component includes: an interposer disposed over the package substrate; a first die disposed along the interposer; and a second die disposed along the interposer, the second die being laterally adjacent the first die; attaching a first thermal interface material to the first die, the first thermal interface material being composed of a first material; attaching a second thermal interface material to the second die, the second thermal interface material being composed of a second material different from the first material; and attaching a lid assembly to the package substrate, the lid assembly being further attached to the first thermal interface material and the second thermal interface material.Type: ApplicationFiled: January 6, 2023Publication date: April 18, 2024Inventors: Chang-Jung Hsueh, Po-Yao Lin, Hui-Min Huang, Ming-Da Cheng, Kathy Yan
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Publication number: 20240128219Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: December 6, 2023Publication date: April 18, 2024Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
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Patent number: 11961817Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.Type: GrantFiled: July 8, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai Jun Zhan, Chang-Jung Hsueh, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
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Publication number: 20240096787Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Ming-Da CHENG, Wei-Hung LIN, Hui-Min HUANG, Chang-Jung HSUEH, Po-Hao TSAI, Yung-Sheng LIN
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Publication number: 20240088119Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
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Publication number: 20180166367Abstract: A flip-chip packaging diode with a multichip structure includes at least two flip-chips arranged with an interval apart from each other and horizontally disposed on the top of a lower guide plate, and each flip-chip has a bottom electrically connected to the lower guide plate and a top having a conductive layer. An insulating material is filled between the two flip-chips and at the outer periphery of the two flip-chips, so that the conductive layers at the tops of the two flip-chips are isolated to form a first electrode and a second electrode for electrically connecting an external circuit. With this structure, a series circuit is formed between the two flip-chips.Type: ApplicationFiled: January 6, 2017Publication date: June 14, 2018Applicant: FORMOSA MICROSEMI CO., LTD.Inventors: Wen-Hu WU, Chien-Wu CHEN, His-Piao LAI, Hui-Min LIN
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Patent number: 9847225Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.Type: GrantFiled: November 15, 2011Date of Patent: December 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Fai Cheng, An-Shen Chang, Hui-Min Lin, Tsz-Mei Kwok, Hsien-Ching Lo
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Patent number: 9799750Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.Type: GrantFiled: July 17, 2012Date of Patent: October 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Fai Cheng, Han-Ting Tsai, An-Shen Chang, Hui-Min Lin
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Patent number: 9543210Abstract: A method includes forming a first mask over a substrate through a double patterning process, wherein the first mask comprises a horizontal portion and a plurality of vertical portions protruding over the horizontal portion, and wherein the vertical portions are spaced apart from each other, applying a first etching process to the first mask until a top surface of a portion of the substrate is exposed, applying a second etching process to the substrate to form intra-device openings and inter-device openings, wherein the inter-device openings are formed at the exposed portion of the substrate, filling the inter-device openings and the intra-device openings to form inter-device insulation regions and intra-device insulation regions and etching back the inter-device insulation regions and the intra-device insulation regions to form a plurality of fins protruding over top surfaces of the inter-device insulation regions and the intra-device insulation regions.Type: GrantFiled: September 5, 2015Date of Patent: January 10, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
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Publication number: 20150380315Abstract: A method includes forming a first mask over a substrate through a double patterning process, wherein the first mask comprises a horizontal portion and a plurality of vertical portions protruding over the horizontal portion, and wherein the vertical portions are spaced apart from each other, applying a first etching process to the first mask until a top surface of a portion of the substrate is exposed, applying a second etching process to the substrate to form intra-device openings and inter-device openings, wherein the inter-device openings are formed at the exposed portion of the substrate, filling the inter-device openings and the intra-device openings to form inter-device insulation regions and intra-device insulation regions and etching back the inter-device insulation regions and the intra-device insulation regions to form a plurality of fins protruding over top surfaces of the inter-device insulation regions and the intra-device insulation regions.Type: ApplicationFiled: September 5, 2015Publication date: December 31, 2015Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
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Patent number: 9130058Abstract: A device includes a plurality of intra-device insulation regions having a first height; and a plurality of semiconductor fins horizontally spaced apart from each other by the plurality of intra-device insulation regions. A portion of the plurality of semiconductor fins is disposed above the plurality of intra-device insulation regions. The device further includes a first inter-device insulation region and a second inter-device insulation region with the plurality of semiconductor fins disposed therebetween. The first and the second inter-device insulation regions have a second height greater than the first height.Type: GrantFiled: September 1, 2010Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Ping Chen, Hui-Min Lin, Ming-Jie Huang, Tung Ying Lee
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Publication number: 20140021517Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. An isolation structure is formed in a substrate and a gate stack is formed atop the isolation structure. A spacer is formed adjoining a sidewall of the gate stack and extends beyond an edge of the isolation structure. The disclosed method provides an improved method for protecting the isolation structure by using the spacer. The spacer can prevent the isolation structure from being damaged by chemicals, therefor, to enhance contact landing and upgrade the device performance.Type: ApplicationFiled: July 17, 2012Publication date: January 23, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Fai Cheng, Han-Ting Tsai, An-Shen Chang, Hui-Min Lin
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Patent number: 8497001Abstract: A first substrate and a second substrate are provided. An alignment process is performed on a surface of the first substrate and a surface of the second substrate respectively. A liquid crystal mixture is prepared, where the liquid crystal mixture includes a liquid crystal molecule and a liquid crystal monomer having a functional group of diacrylates, and the liquid crystal monomer having the functional group of diacrylates occupies 0.01-2 wt % of the liquid crystal mixture. The first substrate and the second substrate are assembled, and the liquid crystal mixture is filled therebetween. A polymerization curing process is performed such that the liquid crystal monomer having the functional group of diacrylates is polymerized to respectively form a liquid crystal polymer film on the aligned surfaces of the first and second substrates. The method enhances anchoring energy and reduces problems of V-T shift, surface gliding, and residual image.Type: GrantFiled: November 2, 2012Date of Patent: July 30, 2013Assignees: Taiwan TFT LCD Association, Chunghwa Picture Tubes, Ltd., AU Optronics Corporation, Hannstar Display Corporation, Chi Mei Optoelectronics Corporation, Industrial Technology Research InstituteInventors: Cho-Ying Lin, Ding-Jen Chen, Hui-Min Lin, Yang-Ching Lin
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Publication number: 20130119444Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.Type: ApplicationFiled: November 15, 2011Publication date: May 16, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Fai CHENG, An-Shen CHANG, Hui-Min LIN, Tsz-Mei KWOK, Hsien-Ching LO
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Publication number: 20130056890Abstract: A first substrate and a second substrate are provided. An alignment process is performed on a surface of the first substrate and a surface of the second substrate respectively. A liquid crystal mixture is prepared, where the liquid crystal mixture includes a liquid crystal molecule and a liquid crystal monomer having a functional group of diacrylates, and the liquid crystal monomer having the functional group of diacrylates occupies 0.01-2 wt % of the liquid crystal mixture. The first substrate and the second substrate are assembled, and the liquid crystal mixture is filled therebetween. A polymerization curing process is performed such that the liquid crystal monomer having the functional group of diacrylates is polymerized to respectively form a liquid crystal polymer film on the aligned surfaces of the first and second substrates. The method enhances anchoring energy and reduces problems of V-T shift, surface gliding, and residual image.Type: ApplicationFiled: November 2, 2012Publication date: March 7, 2013Inventors: Cho-Ying Lin, Ding-Jen Chen, Hui-Min Lin, Yang-Ching Lin
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Patent number: 8325304Abstract: A first substrate and a second substrate are provided. An alignment process is performed on a surface of the first substrate and a surface of the second substrate respectively. A liquid crystal mixture is prepared, where the liquid crystal mixture includes a liquid crystal molecule and a liquid crystal monomer having a functional group of diacrylates, and the liquid crystal monomer having the functional group of diacrylates occupies 0.01-2 wt % of the liquid crystal mixture. The first substrate and the second substrate are assembled, and the liquid crystal mixture is filled therebetween. A polymerization curing process is performed such that the liquid crystal monomer having the functional group of diacrylates is polymerized to respectively form a liquid crystal polymer film on the aligned surfaces of the first and second substrates. The method enhances anchoring energy and reduces problems of V-T shift, surface gliding, and residual image.Type: GrantFiled: November 30, 2009Date of Patent: December 4, 2012Assignees: Taiwan TFT LCD Association, Chunghwa Picture Tubes, Ltd., AU Optronics Corporation, Hannstar Display Corporation, Chi Mei Optoelectronics Corporation, Industrial Technology Research InstituteInventors: Cho-Ying Lin, Ding-Jen Chen, Hui-Min Lin, Yang-Ching Lin