Abstract: A stacked aluminum electrolytic capacitor includes a lead frame, a capacitor set, and at least one laser welding area. The lead frame includes a positive electrode end and a negative electrode end spaced from the positive electrode end. The capacitor set includes a plurality of stacked capacitor elements each having a positive electrode portion electrically connected to the positive electrode end and a negative electrode portion electrically connected to the negative electrode end. The at least one laser welding area is configured by a laser source capable of emitting a laser beam to perform laser welding on the positive electrode end and the positive electrode portion to form a fusion connection therebetween.

Abstract: A stacked aluminum electrolytic capacitor includes a lead frame, a capacitor set, and at least one laser welding area. The lead frame includes a positive electrode end and a negative electrode end spaced from the positive electrode end. The capacitor set includes a plurality of stacked capacitor elements each having a positive electrode portion electrically connected to the positive electrode end and a negative electrode portion electrically connected to the negative electrode end. The at least one laser welding area is configured by a laser source capable of emitting a laser beam to perform laser welding on the positive electrode end and the positive electrode portion to form a fusion connection therebetween.

Abstract: The present invention provides a universal vector for expressing a protein in a Cyanobacterium that includes an erythromycin promoter and a homologous recombination DNA fragment, and further provides a transformed E. coli and a genetically modified Cyanobacterium. In addition, the present invention also provides a method for expressing a protein in a Cyanobacterium that includes steps of inserting a gene of a specific protein into the universal vector and transforming the vector into a Cyanobacterium, so as to express the specific protein.

Abstract: A semiconductor package with an enhancing layer is provided. The package includes a leadframe, a chip, several bumps and an enhancing layer. The leadframe includes several leads. Several bonding pads are disposed on a surface of the chip. The bumps connect the bonding pads of the chip and the leads of the leadframe. The enhancing layer covers the leads and the bumps. The enhancing layer including copper is formed by electroplating. Or, the melting point of the enhancing layer is greater than the melting points of lead and tin.

Abstract: A package structure for a multi-chip integrated circuit (IC) is disclosed and the structure includes substrate having a position for bonding with chips for chip-bonding and having at least a hole for the passage of a gold wire in the course of wire-bonding, a first chip attached to the substrate with a chip bonding agent and being wire-bonded on the substrate and the chip bonding position being opposite to the 2nd chip with the substrate in-between, and the gold wire of the wire-bonding passed through the hole of the substrate from the substrate bonding pad at the substrate and on the same lateral side of the second chip and being connected to the pin pad of the first chip, at least a second chip being flip-chip bonded onto the substrate and the bonding position being at different sides of the bonding between the substrate and the first chip, and a package body including filler of the second chip extended to cover the hole of the substrate and the first chip and the gold wire connected to the substrate and th

Abstract: A fabrication method for solder bump pattern of rear section wafer package is disclosed and the method includes the steps of: (a) pattern-etching the wafer at a passivation layer for the positioning of the solder bump; (b) depositing the entire under bump metal layer,

Abstract: A method of wire bonding of a semiconductor device for resolving oxidation of copper bonding pad is disclosed. The method comprises the steps of exposing the copper bonding pad of a wafer which has been completed with semiconductor circuit fabrication; covering the copper bonding pad of the wafer with a protective anti-oxidization film which will be vaporized when heated; performing wire bonding directly without requiring the removal of the protective film, employing ultrasonic vibration energy, pressurizing deformation energy and heat energy in the course of bonding to vaporize the protective film so that the metal wire and the copper pad form a large area intermetallic compound layer for bonding.

Abstract: An open-typed multi-chip stack-packaging is disclosed and the packaging comprises a substrate having a first surface and a second surface, at least a through opening formed on the substrate, and including at least two layers of circuitry to electrically transmit signals; at least a first chip positioned on the upper section of the opening of the first surface and a plurality of protruded blocks being soldered onto the circuitry on the first surface of the substrate at the external region of the substrate for electrically connection; at least a second chip stacked onto the first chip and the second chip being connected electrically to the circuitry of the first surface with gold lines; at least a third chip positioned at the lower section of the opening of the second surface and having a size smaller than the first chip, and a plurality of protruded blocks being used to electrically bond with the center position of the first chip, and adhesive being used to fill the first chip and the third chip, and the regio

Abstract: A semiconductor chip package with cooling arrangement includes a heat sink adapted for covering at least a semiconductor chip, characterized in that said heat sink has an inverted U-shaped cross section thereby forming a recess at an inner bottom thereof adapted for covering at least a semiconductor chip and a plurality of pins extending downwardly from a circumferential lower edge of said heat sink, each of said pins being formed with a neck, an enlarged head, and an open slot separating said neck and said enlarged head into two portions, whereby the package can rapidly remove heat from the semiconductor chip, filter noise and reduce inductance.

Abstract: A fabrication method of semiconductor packaging and the packaging element is disclosed. A layer of copper is formed on a thick heat-resistant tape and the surface of the copper layer is coated with a light sensitive photoresist. A light source passes through a pre-fabricated circuit negative being performed on the copper layer such that the photoresist is retained on the surface of the copper layer. An etching step is performed so as to obtain a copper wire with circuit diagram. After that, a wire bonding or a flip chip method is used to bind copper wire circuit with the chip. An appropriate packaging method is performed, a packaging element is obtained after the heat-resistant tape is removed.

Abstract: A semiconductor chip package with cooling arrangement includes a heat sink adapted for covering at least a semiconductor chip, characterized in that said heat sink has an inverted U-shaped cross section thereby forming a recess at an inner bottom thereof adapted for covering at least a semiconductor chip and a plurality of pins extending downwardly from a circumferential lower edge of said heat sink, each of said pins being formed with a neck, an enlarged head, and an open slot separating said neck and said enlarged head into two portions, whereby the package can rapidly remove heat from the semiconductor chip, filter noise and reduce inductance.

Abstract: A device for making metal bumps includes a hard conical tubular member having a vertical passage which is conical in shape and has a larger diameter at a bottom such that a lower portion of the vertical passage is larger than an upper portion of the vertical passage, whereby a metal wire is inserted into the vertical passage of the hard conical tubular member, with a lower end of the metal wire protruded downwardly out of the vertical passage, the lower end of the metal wire is melted to form a ball, the hard conical tubular member is approached to a raised platform formed on a top of a chip, and a load is applied to the metal wire and the metal wire is heated and bonded on the pad of die and ultrasonic energy is applied to deform the melted metal so as to fill up the lower portion of the vertical passage thereby forming a metal bump on the raised platform of the chip, and finally the hard conical tubular member is removed to pull off the necking position between the metal wire and a top of the metal bump the

Abstract: A device for making metal bumps includes a hard conical tubular member having a vertical conical passage at an upper portion thereof, a bell shaped chamber at a lower portion thereof which is larger than the vertical conical passage in diameter, located under and communicated with the vertical conical passage, and a circular recess which is larger than the bell shaped chamber in diameter, located under and communicated with the bell shaped chamber, thereby forming a capillary tube with a surface.

Abstract: A device for making metal bumps includes a hard conical tubular member having a vertical conical passage at an upper portion thereof, a bell shaped chamber at a lower portion thereof which is larger than the vertical conical passage in diameter, located under and communicated with the vertical conical passage, and a circular recess which is larger than the bell shaped chamber in diameter, located under and communicated with the bell shaped chamber, thereby forming a capillary tube with a surface.

Abstract: The present invention relates to a manufacturing method for multilayer high density substrate. The circuit layout of the first layer substrate of the multilayer board requires a high demand of pitch density, and therefore polyimide layer is used to make into polyimide substrate (or other high density polymeric film substrate), and combines with the non-high density multilayer board formed from second layer board (or more layer boards) made of organic substrate. In making the organic multilayer board, the adjacent surface of the first layer polyimide substrate (or high density polymeric film substrate), corresponding to appropriate solder pad position of the first layer polyimide substrate (or high density polymeric film substrate), is formed with a solder bump. Thus, when the individual layer board and the first layer substrate are combined, direct heating and compression are applied, such that the bump and the solder pad are bound and electrically connected.

Abstract: A method of forming cylindrical bumps on a substrate for integrated circuits includes the steps of: forming copper circuits on a board of a substrate by means of electroplating; covering said board with a screening material; forming openings in said screening material to align with copper circuits on said board, filling pure copper or high melting point metal into said openings by electroplating to form cylindrical projections; forming a layer of solder alloy on an upper end of each of said cylindrical projections to be even with an upper surface of said screening material, and removing said screening material to leave the cylindrical bumps, whereby the engagement operation between the die and the substrate can be facilitated and the manufacture of the die can be easier.

Abstract: A method of forming metal bumps on a wafer includes the steps of adhering a heat-resistant and steady synthetic tape on the top of the wafer, punching holes through the synthetic tape to form a blind hole on the synthetic tape above the under-bump-metallurgy layer (UBM), filling solder paste into the blind hole by a pusher, melting and then cooling the solder paste into a solder block removing the synthetic tape to expose the solder block, and melting the solder block to form a ball-shaped solder bump.

Abstract: A process of manufacturing thin ball array substrates includes the steps of: using a layer of polyimide film as a carrier, electroplating a thin copper layer on the polyimide film, electroplating a thick copper layer on the thin copper layer, applying photosensitive coating layers on both sides of the carrier, mounting two masks with optically transmissible circuit tracks on two sides of the carrier and then processing the carrier with exposure treatment, processing the carrier with development treatment so as to remove the photosensitive coating layers aligned with the circuit track thereby forming recessed circuit tracks on the photosensitive coating layers, electroplating a copper layer on a top of the carrier thereby forming an additional copper layer on the thick copper layer, etching a bottom of the carrier to remove the upper recessed circuit track thereon, coating the copper layer on the upper recessed circuit track with soldering metallic material so as to make a top of the soldering metallic materia