Patents by Inventor Hui Tseng
Hui Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989966Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.Type: GrantFiled: October 8, 2021Date of Patent: May 21, 2024Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hsin-Hui Lee, Han-Liang Tseng, Jiunn-Liang Yu, Kwang-Ming Lin, Yin Chen, Si-Twan Chen, Hsueh-Jung Lin, Wen-Chih Lu, Chih-Hsien Chen
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Patent number: 11988686Abstract: A vertical probe card and a fence-like probe thereof are provided. The fence-like probe has a probe length within a range from 5 mm to 8 mm. The fence-like probe includes a fence-like segment, a ceramic layer, a connection segment, and a testing segment. The fence-like segment has an elongated shape defining a longitudinal direction, and the fence-like segment has a penetrating slot that is formed along the longitudinal direction and that has a length greater than 65% of the probe length. The ceramic layer is directly formed on an outer surface of the fence-like segment and covers two long walls of the penetrating slot. The connection segment and the testing segment are respectively connected to two end portions of the fence-like segment, and is not formed on the connection segment and the testing segment.Type: GrantFiled: November 3, 2022Date of Patent: May 21, 2024Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.Inventors: Wei-Jhih Su, Chao-Hui Tseng, Hao-Yen Cheng, Mei-Hui Chen
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Publication number: 20240162402Abstract: A display device includes a circuit substrate, a plurality of pad sets and a plurality of light-emitting elements. The plurality of pad sets is disposed on the circuit substrate, and each pad set includes a first pad and a second pad surrounding the first pad. The plurality of light-emitting elements is disposed above the circuit substrate, and each light-emitting element includes a first electrode, a second electrode and a light-emitting stack between the first electrode and the second electrode, wherein the first electrode is electrically connected to the first pad, the second electrode is electrically connected to the second pad, and an orthographic projection of the second electrode on the circuit substrate is overlapped with an orthographic projection of the first pad on the circuit substrate.Type: ApplicationFiled: December 28, 2022Publication date: May 16, 2024Applicant: AUO CorporationInventors: Chia-Hui Pai, Wen-Hsien Tseng, Chien-Hung Kuo
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Patent number: 11984353Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.Type: GrantFiled: June 21, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Jhy-Jyi Sze
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Publication number: 20240153987Abstract: The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.Type: ApplicationFiled: January 5, 2024Publication date: May 9, 2024Inventors: Hsuan-Han Tseng, Chun-Yuan Chen, Lu-Sheng Chou, Hsiao-Hui Tseng, Ching-Chun Wang
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Patent number: 11977745Abstract: A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.Type: GrantFiled: August 11, 2022Date of Patent: May 7, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Ming-Hui Tseng, Chia-Lung Ma, Zhen-Yu Weng
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Publication number: 20240145632Abstract: A micro light emitting device includes an epitaxial structure, a conductive layer, and a first insulating layer. The epitaxial structure has a first surface and a second surface opposite to the first surface, and includes a first semiconductor layer, an active layer and a second semiconductor layer that are arranged in such order in a direction from the first surface to the second surface. The conductive layer is formed on a surface of the first semiconductor layer away from the active layer. The first insulating layer is formed on the surface of the first semiconductor layer away from the active layer, and exposes at least a part of the conductive layer.Type: ApplicationFiled: October 23, 2023Publication date: May 2, 2024Inventors: Ming-Chun TSENG, Shaohua HUANG, Hongwei WANG, Kang-Wei PENG, Su-Hui LIN, Xiaomeng LI, Chi-Ming TSAI, Chung-Ying CHANG
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Publication number: 20240144056Abstract: A method includes: obtaining impact values for characteristic conditions; selecting training data subsets respectively from training data sets according to the impact values; obtaining a candidate model and an evaluation value based on the training data subsets; supplementing the training data subsets according to the impact values; obtaining another candidate model and another evaluation value based on training data subsets thus supplemented; repeating the step of supplementing the training data subset, and the step of obtaining another candidate model and another evaluation value based on the training data subsets thus supplemented; and selecting one of the candidate models as a prediction model based on the evaluation values.Type: ApplicationFiled: August 2, 2023Publication date: May 2, 2024Applicants: TAIPEI VETERANS GENERAL HOSPITALInventors: Chin-Chou Huang, Ming-Hui Hung, Ling-Chieh Shih, Yu-Ching Wang, Han Cheng, Yu-Chieh Shiao, Yu-Hsuan Tseng
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Publication number: 20240145498Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.Type: ApplicationFiled: January 4, 2023Publication date: May 2, 2024Inventors: Hao-Lin Yang, Fu-Sheng Kuo, Ching-Chun Wang, Hsiao-Hui Tseng, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
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Patent number: 11963868Abstract: A double-sided aspheric diffractive multifocal lens and methods of manufacturing and design of such lenses in the field of ophthalmology. The lens can include an optic comprising an aspheric anterior surface and an aspheric posterior surface. On one of the two surfaces a plurality of concentric diffractive multifocal zones can be designed. The other surface can include a toric component. The double-sided aspheric surface design results in improvement of the modulation transfer function (MTF) of the lens-eye combination by aberration reduction and vision contrast enhancement as compared to one-sided aspheric lens. The surface having a plurality of concentric diffractive multifocal zones produces a near focus, an intermediate focus, and a distance focus.Type: GrantFiled: May 27, 2021Date of Patent: April 23, 2024Assignee: AST Products, Inc.Inventors: Yi-Feng Chiu, Chuan-Hui Yang, Wen-Chu Tseng
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Publication number: 20240128216Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.Type: ApplicationFiled: January 4, 2023Publication date: April 18, 2024Inventors: Hao-Lin Yang, Kuan-Chieh Huang, Wei-Cheng Hsu, Tzu-Jui Wang, Ching-Chun Wang, Hsiao-Hui Tseng, Chen-Jong Wang, Dun-Nian Yaung
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Publication number: 20240128420Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.Type: ApplicationFiled: December 6, 2022Publication date: April 18, 2024Applicant: AUO CorporationInventors: Chia-Hui Pai, Tai-Tso Lin, Wen-Hsien Tseng, Wei-Chieh Chen, Kuan-Yi Lee, Chih-Chun Yang
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Publication number: 20240115457Abstract: A health care device and a health care method are illustrated, the health care method is used to arrange the health care device at a predetermined location in front of a belly button of a user with a predetermined distance, and to emit the low-frequency wave with a predetermined frequency to the belly button by using a low-frequency wave emitter. The health care device is formed by the low-frequency wave emitter and a cone/pyramid part. The predetermined frequency is 1.27 Hz to 1.81 Hz, and the predetermined distance is 5 cm to 8 cm. The above health care device and method can increase contents of active T cells and B cells in blood and increase an ability of NK cell strains for poisoning cancer cell strains (K562). In short, the above health care device and method have health benefits without a risk of excessive energy causing harm.Type: ApplicationFiled: November 23, 2022Publication date: April 11, 2024Inventors: MING-SHUN LEE, CHIN-SUNG TSENG, HSU-HUI TSENG, HSIEN-CHING TSENG, WEI-LONG LEE
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Patent number: 11953277Abstract: A firing control system with multiple safeties is disclosed. It comprises a base, a return spring, a firing pin releaser, and a trigger connecting bar. The trigger connecting bar is connected with the trigger of the pistol and has a firing safety portion with a T shape. The design of the firing safety portion with a limit protrusion portion of the firing pin releaser of the present invention form a safety mechanism for unintentional discharge of the pistol, which improves the problem that the existing improved products are easy to cause the pistol to fire under an unfired state.Type: GrantFiled: March 2, 2023Date of Patent: April 9, 2024Assignee: FORMOSAN ARSENAL GROUP CO., LTD.Inventor: Shu Hui Tseng
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Patent number: 11957064Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: GrantFiled: October 18, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Patent number: 11948949Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.Type: GrantFiled: July 15, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
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Patent number: 11928358Abstract: A command management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: obtaining a plurality of commands from a memory of a host system; storing the commands in a first buffer region of the memory storage device; in response to a first command and a second command meeting a pairing condition in the first buffer region, putting the first command and the second command in the first buffer region in a first command queue of the memory storage device; and continuously executing the first command and the second command in the first command queue.Type: GrantFiled: February 16, 2022Date of Patent: March 12, 2024Assignee: PHISON ELECTRONICS CORP.Inventor: Ming-Hui Tseng
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Patent number: 11929587Abstract: A dual-wavelength gun aiming collimated beam light source module, comprising: a positioning seat, having a first through hole and a second through hole inside; a first laser module for emitting laser light of first wavelength; a second laser module for emitting laser light of second wavelength; a first reflecting mirror, and the inner surface of the first reflecting mirror has a first wavelength laser light high-reflection coating; and a second reflecting mirror, and the outer surface of the second reflecting mirror has a first wavelength laser light high-reflection coating and a second wavelength laser light high-reflection coating; so as to solve the aiming deviation problem.Type: GrantFiled: October 7, 2021Date of Patent: March 12, 2024Assignee: Arima Lasers Corp.Inventors: Cheng-Tsung Tseng, Ming-Hui Fang
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Publication number: 20240081157Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240074328Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang