Patents by Inventor Hui Wei

Hui Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240172859
    Abstract: The disclosure notably relates to a computer-implemented method for selecting a chemical compound applicable on a class of human hairs. The method comprises obtaining a database storing data relative to chemical compounds. For each compound the data comprises an identifier, an ingredient and a performance score. The method also comprises obtaining assessed hair properties and hair target properties. The method also comprises computing at least one goal score and a manageability goal score from the assessed hair properties and hair target properties. The method also comprises determining at least one identifier in the database satisfying the computed goal score and the computed manageability goal score. The satisfying comprises minimizing a distance function between the computed goal score and a corresponding goal score and maximizing a fit-to-manageability function between the computed manageability goal score and the corresponding manageability score.
    Type: Application
    Filed: August 22, 2023
    Publication date: May 30, 2024
    Inventors: Angel KOH, Hui Min LEE, Chun Wei TAN, Max MORINI
  • Publication number: 20240173924
    Abstract: Systems and methods for error reduction in three-dimensional (3D) printing are provided and can include automatically adjusting printing parameters (for example, printing speed, acceleration, extrusion rate, and/or any other parameters) in the “G-codes” for a 3D printer (for example, fused deposition modeling) to compensate for printing errors that may occur when printing is performed at a high speed. An algorithm can be used to increase printing speed while mitigating reductions in printing quality.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 30, 2024
    Inventors: Hui Wang, An-Tsun Wei
  • Patent number: 11995390
    Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Jerry Chang Jui Kao, Pin-Dai Sue, Jiun-Jia Huang, Yu-Ti Su, Wei-Hsiang Ma
  • Publication number: 20240168110
    Abstract: The present application relates to a technical field of determining an irreversible demagnetization of a grain boundary diffusion NdFeB magnet, and more particularly, to a method for identifying an irreversible demagnetization of a grain boundary diffusion NdFeB magnet by magnetic field distribution. After applying a reverse magnetic field to a saturatedly magnetized grain boundary diffusion NdFeB magnet, if a number of magnetic poles on a non-diffusion face of the grain boundary diffusion NdFeB magnet is increased, it is determined that there is an irreversible demagnetization in the grain boundary diffusion NdFeB magnet.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 23, 2024
    Inventors: Jinghui DI, Huiqiang LIU, Xiongfei WU, Shengli JIA, Hui MENG, Qifeng WEI
  • Patent number: 11991853
    Abstract: A clip for securing one or more cables associated with a computing device includes a baseplate, a first wall, and a second wall. The first wall and the second wall extend from the baseplate. The first wall has a first inward projection at a distal end thereof. The second wall has a second inward projection at a distal end thereof. The first wall is generally parallel to the second wall. The first wall and the second wall are spaced apart from each other by an interior space configured to receive the one or more cables. The first inward projection and the second inward projection aid in preventing the one or more cables from moving outside of the interior space.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: May 21, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Wei Lin, Jui-Chung Lee, Hui-Ying Suk
  • Patent number: 11987566
    Abstract: The present invention provides a novel compound for effectively preventing nerve damage and protecting nerves, and a preparation method thereof. Besides, the present invention also provides a pharmaceutical composition comprising the novel compound, and a use of the novel compound for preventing nerve damage and protecting nerves.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: May 21, 2024
    Assignee: GENHEALTH PHARMA CO., LTD.
    Inventors: Lain-Tze Lee, Hui-Ping Tsai, Yi-Wen Lin, Shu-Fen Huang, Shih-Hung Liu, Chin-Wei Liu, Pi-Tsan Huang, Mei-Hui Chen
  • Patent number: 11990383
    Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang, Chia-Wei Wang
  • Publication number: 20240162150
    Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of gate strips, wherein each gate strip is arranged to be a gate terminal of a transistor; forming a plurality of first metal strips above the plurality of gate strips; and forming a plurality of second metal strips above the plurality of first metal strips, wherein the plurality of second metal strips are co-planar, and each second metal strip and one of the first metal strips are crisscrossed from top view; wherein a length between two adjacent gate strips is twice as a length between two adjacent second metal strips, and a length of said one of the first metal strips is smaller than two and a half times as the length between two adjacent gate strips.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Inventors: SHIH-WEI PENG, HUI-TING YANG, WEI-CHENG LIN, JIANN-TYNG TZENG
  • Patent number: 11981467
    Abstract: An apparatus and a method for importing fluid, and a method for tearing film are provided. The apparatus imports fluid into a product and tears a breathable film covered on the product, the product defines a vent in a surface, the breathable film covers on the vent. The apparatus includes a transfer assembly and a controller. The breathable film is connected to the transfer assembly. The controller is coupled to the transfer assembly and configured to control the transfer assembly to vertically move relative to the surface of the product to tear the breathable film from the vent.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: May 14, 2024
    Assignee: SHENZHENSHI YUZHAN PRECISION TECHNOLOGY CO., LTD.
    Inventors: Hui-Tse Yu, Chen-Yu Hong, Zhi-Chao Xu, Ya-Wei Zeng
  • Patent number: 11981669
    Abstract: A compound represented by formula (I) or a tautomer, an optical isomer, a nitrogen oxide, a solvate, a pharmaceutically acceptable salt or prodrug thereof are useful for treating or relieving an HIF-related and/or EPO-related disease or condition in patient. The preparation method for the compound, and use of a drug composition containing the compound and the compound or the drug composition in preparation of a drug are also provided.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 14, 2024
    Assignee: CSPC ZHONGQI PHARMACEUTICAL TECHNOLOGY (SHIJIAZHUANG) CO., LTD
    Inventors: Yan Zhang, Miaomiao Wei, Xuejiao Zhang, Guorui Mi, Hui An, Bing Wei, Qian Guo
  • Patent number: 11983479
    Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
  • Publication number: 20240153890
    Abstract: The semiconductor package substrate module including a substrate, a plurality of first wires, at least one second wire, a chip, and an encapsulating body, wherein the first wires electrically connect to a first electrical contact point of the substrate and a second electrical contact point of the chip. Besides, one end of the at least one second wire connects to the at least one grounding transfer area or a first ground contact point of the substrate, and another end of the second wire extends toward a cutting area. The encapsulating body encapsulates the substrate, the first and second wires, and the chip. The semiconductor package substrate module is cut and separated along the cutting area of the substrate to form a plurality of semiconductor packaging components. A side surface of the encapsulating body exposes the first wires or at least one second wire of each semiconductor packaging component.
    Type: Application
    Filed: March 30, 2023
    Publication date: May 9, 2024
    Inventors: Chia Fong CHOU, Ta Wei CHOU, Hui-Lung HSU
  • Publication number: 20240153896
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11979782
    Abstract: A method for transfer between communications systems includes establishing at least one first data connection channel in a first communications system, selecting at least one second data connection channel from the at least one first data connection channel, where the second data connection channel is included in the first data connection channel and is certain to support transfer from the first communications system to a second communications system or is uncertain whether to support transfer from the first communications system to the second communications system, and transferring the second data connection channel to the second communications system when the terminal device has been transferred from the first communications system to the second communications system.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: May 7, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hui Jin, Zhenrong Wei, Fenghui Dou
  • Publication number: 20240145878
    Abstract: An electrode structure of rechargeable battery includes a battery tab stack, an electrode lead, a welding protective layer and a welding seam. The battery tab stack is formed by extension of a plurality of electrode sheets. The electrode lead is joined to one side of the battery tab stack. The welding protective layer is joined to another side of the battery tab stack opposite to the electrode lead. The welding seam extends from the welding protective layer to the electrode lead through the battery tab stack.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 2, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kun-Tso CHEN, Tsung-Ying TSAI, Tsai-Chun LEE, Chih-Wei CHIEN, Hui-Ta CHENG
  • Publication number: 20240143888
    Abstract: An integrated circuit includes a first and second active region, a first insulating region, and a first and second contact. The first and second active region extend in a first direction, and are on a first level. The first active region includes a first and second drain/source region. The second active region includes a third drain/source region. The first insulating region is over the first drain/source region. The first contact overlaps the third drain/source region, is electrically coupled to the third drain/source region and is located on a second level. The second contact includes a first and second portion. The first portion overlaps the first and second drain/source. The second portion overlaps the first contact, the first and third drain/source region, and the first insulating region, and is electrically coupled to the first portion, and electrically insulated from the first drain/source region.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Pochun WANG, Yu-Jung CHANG, Hui-Zhong ZHUANG, Ting-Wei CHIANG
  • Publication number: 20240132869
    Abstract: Disclosed herein are compositions and methods for making and using improved carbonic anhydrases for novel, sustainable, and low energy CO2 waste gas scrubbing technologies that are also transformational carbon capture technologies. Embodiments of methods, systems and compositions disclosed herein include, but are not limited to, non-aqueous solvents, advanced membranes, sorbents, and cryogenic systems that significantly reduce the cost of CO2 capture from coal and natural gas-fired power plants and industrial facilities. Methods disclosed herein reduce the energy and cost required for CO2 separation and can be applied for both pre-combustion and post-combustion CO2 capture.
    Type: Application
    Filed: February 22, 2022
    Publication date: April 25, 2024
    Inventors: Min ZHANG, Vladimir Vladimirovich LUNIN, Hui WEI
  • Patent number: 11967596
    Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 11964358
    Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang
  • Patent number: D1024051
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng