Abstract: The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.

Abstract: A power-on screen pattern correcting apparatus is for correcting start output data of output terminals of a source driver such that a power-on screen pattern of a display is substantially uniform. The correcting apparatus comprises a flip-flop, a first logic unit and a second logic unit. The flip-flop controls a level of an inner signal to be substantially equal to a low signal level in response to a low level of a power start signal. The first logic unit enables a first signal in response to the low level of the inner signal or a low level of a high-impedance control signal. The second logic unit enables a second signal such that the output terminals are coupled to a charge sharing line and the power-on screen pattern is uniform in response to the low level of the inner signal or a low level of a charge-sharing control signal.

Abstract: An output buffer including a first switch circuit and a buffer is provided. The first switch circuit receives first and second input signals. The buffer circuit includes first and second input stages, first and second output stages and a second switch circuit. The first and the second input stages are coupled to the first switch circuit. The first and the second output stages are coupled to the second switch circuit. The second switch circuit, coupled to the first and the second input stages and the first and the second output stages, selectively couples one of first and the second input stages to the first output stage and selectively couples the other to the second output stage. The first switch circuit further selectively provides one of the first and the second input signals to the first input stage and selectively provides the other to the second input stage.

Abstract: The invention discloses a source driver. The source driver comprises a plurality of channels and a control module. Each of the plurality of channels comprises an output buffer, an output pad, a driving switch, and a charge sharing switch. The control module is used to control a gate signal of the driving switch or the charge sharing switch in each channel to be changed linearly. By doing so, a peak current generated by the source driver can be lowered to reduce the electromagnetic interference (EMI).

Abstract: A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.

Abstract: A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.

Abstract: The invention discloses a controlling apparatus for a signal outputting circuit in an electronic system. The controlling apparatus includes a detecting circuit, a switch, and a controlling circuit. The detecting circuit is used for detecting whether the electronic system has an abnormal condition. The switch is electrically connected between a signal receiving terminal and the signal outputting circuit. The controlling circuit is electrically connected between the detecting circuit and the switch. Once the detecting circuit detects that the electronic system has the abnormal condition, the controlling circuit sets the switch into a high-impedance state.

Abstract: A shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to the flip-flop according to a first selection signal, wherein before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the flip-flop according to the first selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal.

Abstract: A digital-to-analog (D/A) converter comprises a decoder apparatus and an operational amplifier. The decoder apparatus comprises first and second decoder unit. The first decoder unit selects a voltage of first voltage set as first and second voltage in response to a value of first gray level set. The second decoder unit selects first border voltage of second voltage set as the first and the second voltages and second border voltage of that as the first and the second voltages in response to the maximum and the minimum value of second gray level set respectively. The second decoder unit further selects the first and the second boarder voltage as the first and the second voltage respectively in response to an intermediate value of the second gray level set. The operational amplifier generates a pixel voltage having level between the first and the second voltage accordingly.

Abstract: A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents.

Abstract: A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.

Abstract: A power-on screen pattern correcting apparatus is for correcting start output data of output terminals of a source driver such that a power-on screen pattern of a display is substantially uniform. The correcting apparatus comprises a flip-flop, a first logic unit and a second logic unit. The flip-flop controls a level of an inner signal to be substantially equal to a low signal level in response to a low level of a power start signal. The first logic unit enables a first signal in response to the low level of the inner signal or a low level of a high-impedance control signal. The second logic unit enables a second signal such that the output terminals are coupled to a charge sharing line and the power-on screen pattern is uniform in response to the low level of the inner signal or a low level of a charge-sharing control signal.

Abstract: A process for eliminating an interface layer between a poly plug and a hemispherical silicon grain. A substrate comprising a conductive plug and a storage node opening is provided, and the storage node opening is located on the conductive plug. Then, a first conductive layer is formed conformably over the inside surface of the storage node opening and a hemispherical silicon grain layer is formed on the first conductive layer. Next, the hemispherical silicon grain layer and the first conductive layer is implanted and the substrate is annealed. The re-arrangement and re-crystallization of the interface layer can greatly reduce the resistance of the node contact.