Patents by Inventor Huichu Liu
Huichu Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10749104Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.Type: GrantFiled: December 12, 2018Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Huichu Liu, Daniel Morris, Tanay Karnik, Sasikanth Manipatruni, Kaushik Vaidyanathan, Ian Young
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Publication number: 20200228137Abstract: Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Gautham Chinya, Debabrata Mohapatra, Arnab Raha, Huichu Liu, Cormac Brick
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Publication number: 20200194663Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Huichu Liu, Daniel Morris, Tanay Karnik, Sasikanth Manipatruni, Kaushik Vaidyanathan, Ian Young
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Publication number: 20200134417Abstract: Example apparatus disclosed herein include an array of processor elements, the array including rows each having a first number of processor elements and columns each having a second number of processor elements. Disclosed example apparatus also include configuration registers to store descriptors to configure the array to implement a layer of a convolutional neural network based on a dataflow schedule corresponding to one of multiple tensor processing templates, ones of the processor elements to be configured based on the descriptors to implement the one of the tensor processing templates to operate on input activation data and filter data associated with the layer of the convolutional neural network to produce output activation data associated with the layer of the convolutional neural network. Disclosed example apparatus further include memory to store the input activation data, the filter data and the output activation data associated with the layer of the convolutional neural network.Type: ApplicationFiled: December 24, 2019Publication date: April 30, 2020Inventors: Debabrata Mohapatra, Arnab Raha, Gautham Chinya, Huichu Liu, Cormac Brick, Lance Hacking
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Publication number: 20200105833Abstract: A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Jack T. KAVALIEROS, Ian A. YOUNG, Ram KRISHNAMURTHY, Ravi PILLARISETTY, Sasikanth MANIPATRUNI, Gregory CHEN, Hui Jae YOO, Van H. LE, Abhishek SHARMA, Raghavan KUMAR, Huichu LIU, Phil KNAG, Huseyin SUMBUL
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Publication number: 20200098415Abstract: Described is an apparatus to reduce or eliminate imprint charge, wherein the apparatus which comprises: a source line; a bit-line; a memory bit-cell coupled to the source line and the bit-line; a first multiplexer coupled to the bit-line; a second multiplexer coupled to the source-line; a first driver coupled to the first multiplexer; a second driver coupled to the second multiplexer; and a current source coupled to the first and second drivers.Type: ApplicationFiled: July 23, 2018Publication date: March 26, 2020Applicant: Intel CorporationInventors: Huichu Liu, Sasikanth Manipatruni, Ian A. Young, Tanay Karnik, Daniel H. Morris, Kaushik Vaidyanathan
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Publication number: 20200091414Abstract: An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.Type: ApplicationFiled: September 13, 2018Publication date: March 19, 2020Inventors: Huichu Liu, Sasikanth Manipatruni, Daniel Morris, Kaushik Vaidyanathan, Tanay Karnik, Ian Young
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Publication number: 20200091407Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.Type: ApplicationFiled: September 13, 2018Publication date: March 19, 2020Inventors: Huichu LIU, Tanay KARNIK, Sasikanth MANIPATRUNI, Daniel MORRIS, Kaushik VAIDYANATHAN, Ian YOUNG
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Patent number: 10331582Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.Type: GrantFiled: February 13, 2017Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: Ishwar S. Bhati, Huichu Liu, Jayesh Gaur, Kunal Korgaonkar, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Hong Wang, Ian A. Young
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Patent number: 10261923Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.Type: GrantFiled: July 26, 2017Date of Patent: April 16, 2019Assignee: Intel CorporationInventors: Kaushik Vaidyanathan, Daniel H. Morris, Uygar E. Avci, Ian A. Young, Tanay Karnik, Huichu Liu
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Publication number: 20190043549Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.Type: ApplicationFiled: September 27, 2018Publication date: February 7, 2019Inventors: Kaushik Vaidyanathan, Daniel H. Morris, Huichu Liu, Dileep J. Kurian, Uygar E. Avci, Tanay Karnik, Ian A. Young
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Publication number: 20190034360Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.Type: ApplicationFiled: July 26, 2017Publication date: January 31, 2019Inventors: Kaushik VAIDYANATHAN, Daniel H. MORRIS, Uygar E. AVCI, Ian A. YOUNG, Tanay KARNIK, Huichu LIU
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Publication number: 20190013063Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.Type: ApplicationFiled: March 23, 2016Publication date: January 10, 2019Applicant: Intel CorporationInventors: Huichu LIU, Sasikanth MANIPATRUNI, Daniel H. MORRIS, Kaushik VAIDYANATHAN, Niloy MUKHERJEE, Dmitri E. NIKONOV, Ian YOUNG, Tanay KARNIK
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Publication number: 20180285268Abstract: In one embodiment, a processor comprises a processing core, a last level cache (LLC), and a mid-level cache. The mid-level cache is to determine that an idle indicator has been set, wherein the idle indicator is set based on an amount of activity at the LLC, and based on the determination that the idle indicator has been set, identify a first cache line to be evicted from a first set of cache lines of the mid-level cache and send a request to write the first cache line to the LLC.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Kunal Kishore Korgaonkar, Ishwar S. Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Hong Wang, Ian A. Young
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Publication number: 20180232311Abstract: A processor includes a processing core and a cache controller including a read queue and a separate write queue. The read queue is to buffer read requests of the processing core to a non-volatile memory, last level cache (NVM-LLC), and the write queue is to buffer write requests to the NVM-LLC. The cache controller is to detect whether the write queue is full. The cache controller further prioritizes a first order of sending requests to the NVM-LLC when the write queue contains an empty slot, the first order specifying a first pattern of sending the read requests before the write requests, and prioritizes a second order of sending requests to the NVM-LLC in response to a determination that the write queue is full, the second order specifying a second pattern of alternating between sending a write request from the write queue and a read request from the read queue.Type: ApplicationFiled: February 13, 2017Publication date: August 16, 2018Inventors: Ishwar S. Bhati, Huichu Liu, Jayesh Gaur, Kunal Korgaonkar, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Hong Wang, Ian A. Young
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Publication number: 20170345496Abstract: An apparatus is provided which comprises: a select line; a select transistor coupled to a resistive memory element and to the select line; a word-line coupled to a gate terminal of the select transistor; and a current mirror operable to be coupled to the select line during a first mode and to be de-coupled during a second mode.Type: ApplicationFiled: May 25, 2016Publication date: November 30, 2017Inventors: Huichu LIU, Daniel H. MORRIS, Sasikanth MANIPATRUNI, Kaushik VAIDYANATHAN, Ian A. YOUNG, Tanay KARNIK
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Patent number: 9800094Abstract: Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.Type: GrantFiled: May 14, 2015Date of Patent: October 24, 2017Assignee: The Penn State Research FoundationInventors: Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok Kim, Xueqing Li, Alexandre Schmid, Mahsa Shoaran, Unsuk Heo
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Publication number: 20170287555Abstract: An apparatus is described that includes a resistive random access memory cell having a word line that is to receive a narrowed word line signal that limits an amount of time that an access transistor is on so as to limit the cell's high resistive state and/or the cell's low resistive state. Another apparatus is described that includes a resistive random access memory cell having SL and BL lines that are to receive respective signals having different voltage amplitudes to reduce source degeneration effects of the resistive random access memory cell's access transistor. Another apparatus is described that includes a resistive random access memory cell having a storage cell comprising a bottom-side OEL layer. Another apparatus is described that includes a resistive random access memory cell having a storage cell within a metal layer that resides between a pair of other metal layers where parallel SL and BL lines of the resistive random access memory cell respectively reside.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: HUICHU LIU, SASIKANTH MANIPATRUNI, IAN A. YOUNG, TANAY KARNIK, DANIEL H. MORRIS, KAUSHIK VAIDYANATHAN
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Patent number: 9391068Abstract: A power rectifier includes a stage having a first Tunneling Field-Effect Transistor (“TFET”) having a source, a gate, and a drain, a second TFET having a source, a gate, and a drain, a third TFET having a source, a gate, and a drain, and a fourth TFET having a source, a gate, and a drain such that the source of the first TFET, the source of the second TFET, the gate of the third TFET, and the gate of the fourth TFET are connected, the gate of the first TFET, the gate of the second TFET, the source of the third TFET and the source of the fourth TFET are connected, the drain of the first TFET and the drain of the third TFET are connected, and the drain of the second TFET and the drain of the fourth TFET are connected. Alternative embodiments are also disclosed.Type: GrantFiled: August 11, 2014Date of Patent: July 12, 2016Assignee: The Penn State Research FoundationInventors: Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta
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Publication number: 20150333534Abstract: Disclosed are low power electronic devices configured to exploit the sub-threshold swing, unidirectional tunneling, and low-voltage operation of steep slope-tunnel tunnel field-effect transistors (TFET) to improve power-conversion efficiency and power-efficiency of electrical systems incorporating the TFET as an electrical component to perform energy harvesting, signal processing, and related operations. The devices include a HTFET-based rectifier having various topologies, a HTFET-based DC-DC charge pump converter, a HTFET-based amplifier having an amplifier circuit including a telescopic operational transconductance amplifier, and a HTFET-based SAR A/D converter having a HTFET-based transmission gate DFF. Any one of the devices may be used to generate a RF-powered system with improved power conversion efficiencies of power harvesters and power efficiencies of processing components within the system.Type: ApplicationFiled: May 14, 2015Publication date: November 19, 2015Inventors: Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok Kim, Xueqing Li, Alexandre Schmid, Mahsa Shoaran, Unsuk Heo