Patents by Inventor Hui-Chung Wu

Hui-Chung Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967596
    Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guo-Huei Wu, Shih-Wei Peng, Wei-Cheng Lin, Hui-Zhong Zhuang, Chih-Liang Chen, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 11968840
    Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yong-Jie Wu, Yen-Chung Ho, Hui-Hsien Wei, Chia-Jung Yu, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240096706
    Abstract: The present disclosure provides a method of forming a semiconductor device. The method includes: forming an interconnect structure over a substrate; forming a first gate structure and a second gate structure in a first layer of the interconnect structure; forming a first metal oxide layer and a second metal oxide layer in a second layer of the interconnect structure over the first gate structure and the second gate structure, respectively; forming an implant mask over the first metal oxide layer and the second metal oxide layer, the implant mask having different thicknesses corresponding to the first metal oxide layer and the second oxide layer; and performing an implantation operation on the first metal oxide layer and the second metal oxide layer.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 21, 2024
    Inventors: YEN-CHUNG HO, YONG-JIE WU, HUI-HSIEN WEI
  • Publication number: 20100035300
    Abstract: A cis-TEVP fusion protein including a TEVP protease, a TEVP cleavage site and a target protein provide a platform for expression of the target protein. A trans-TEVP fusion protein including a TEVP cleavage site and a target protein, the amino-terminal portion of the target protein adjacent to the C-terminal portion of the TEVP cleavage site, the amino acidic residue in position P2 of the TEVP cleavage site being a Valine also produces the target protein by the same process. A cis-TEVP fusion protein system comprising the first fusion protein and a suitable host cell; a trans-TEVP fusion protein system comprising the second fusion protein and a suitable host cell; associated methods to produce target proteins, and kits of parts are also disclosed herein.
    Type: Application
    Filed: February 27, 2006
    Publication date: February 11, 2010
    Inventors: Andrew H.-J. Wang, Ting-Fang Wang, Yan-Ping Shih, Hui-Chung Wu, Su-Ming Hu
  • Publication number: 20080271837
    Abstract: An adhesive tape adhering device includes a table unit, a wafer bearing unit, an adhesive tape pull-tight unit, an adhesive tape clipping unit, and a rolling unit. The wafer bearing unit movably disposes on the table unit upwardly and downwardly for bearing a wafer. The adhesive tape pull-tight unit has a bundle of adhesive tape, and the adhesive tape pull-tight unit disposes on the table unit and next to one side of the wafer bearing unit. The adhesive tape clipping unit disposes on the table unit and next to the other side of the wafer bearing unit for tightly clipping an end side of a tape of the bundle of adhesive tape.
    Type: Application
    Filed: May 2, 2007
    Publication date: November 6, 2008
    Inventors: Hui-Chung Wu, Hsun-Min Lee
  • Publication number: 20060219167
    Abstract: An apparatus and method of vacuum metallic sintering for a semiconductor uses a quartz tube, a vacuum air-extracting apparatus, a furnace and a gas injection pipe. The metal sintered does not produce metal oxide in a vacuum established by the vacuum air-extracting apparatus. After sintering, a movable furnace can withdraw from the quartz tube immediately to decrease cooling time.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Hung-Lung Cheng, Hui-Chung Wu, Chi-Chen Lee