Abstract: Provided are a binder composition, an electrode, a battery and a power consuming device. The binder composition comprises a fluoropolymer A and a copolymer B, wherein the copolymer B comprises a structural unit derived from a monomer containing a cyano group and a structural unit derived from a monomer containing an ester group. The binder of the present application has a strong bonding force, and the cycling performance of the secondary battery comprising same is excellent.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.

Abstract: The present disclosure provides a determining device for the weathering resistant capability of clastic rocks in a tunnel based on feldspar features, which overcomes the shortcomings of current evaluation methods, is easy to operate, can be used to detect the type, content, and crystal structure of feldspar in a rock stratum, and integrates the information by combining a computer deep learning method to determine the weathering resistant capability of clastic rocks containing different types of feldspar in a tunnel, with high accuracy.

Abstract: Systems and methods of rendering effects are described herein. A computing device can receive a user selection of an effect to be applied during gameplay of a computer game. The computing device can initiate a framework with which to apply the effect during the gameplay. The computing device can determine scenes during the gameplay to apply the effect through the framework. The computing device can determine graphical elements in the scenes that correspond to non-user interface elements through the framework. The computing system can apply the effect to the graphical elements through the framework.

Abstract: Provided is a packaging structure for packaging a display device, the packaging structure comprising: at least one composite film layer, wherein the composite film layer comprises an inorganic pattern and an organic pattern, the inorganic pattern comprises a plurality of curved structures arranged at intervals, the organic pattern comprises a first organic sub-pattern, and the first organic sub-pattern and the inorganic pattern are located in a same layer and are complementary in position; and wherein an orthographic projection of the composite film layer onto the display device at least covers a display area of the display device. A display substrate, a display apparatus, and a method for packaging a display device are also provided.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals, where the active region includes a source, a drain, and a channel region; a word line, where the word line is connected to the channel region and extends along a first direction; a bit line, where the bit line is connected to the drain or the source and extends along a second direction, the first direction being different from the second direction; and a magnetic memory cell, connected to the source or the drain.

Abstract: The present disclosure provides a semiconductor structure, a method of reading data from the semiconductor structure, and a method of writing data into the semiconductor structure. The semiconductor structure includes: a memory matrix, including a plurality of magnetic storage domains arranged in a staggered manner and including a first end, a second end, and an intermediate portion; and a reading and writing circuit, connected to the intermediate portion of the memory matrix and configured to write data into the magnetic storage domains and read data from the magnetic storage domains.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof, including: a substrate; a plurality of transistors, arranged based on a first preset pattern; a plurality of transistor contact structures, corresponding to the transistors, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of which are arranged based on the shape of a regular hexagon; a plurality of memory cells, corresponding to the transistor contact structures, the memory cells are arranged based on the shape of a regular hexagon; and a plurality of memory contact structures, corresponding to the memory cells, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of which are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a transistor; a first phase change memory structure, a bottom electrode of the first phase change memory structure being electrically connected to a first terminal (source or drain) of the transistor; a second phase change memory structure, a top electrode of the second phase change memory structure being electrically connected to the first terminal of the transistor; a first bit line, electrically connected to a top electrode of the first phase change memory structure; and a second bit line, electrically connected to a bottom electrode of the second phase change memory structure.

Abstract: The invention “use of biomarker or biomarkers combination in preparing a diagnostic reagent for fulminant myocarditis and a drug for fulminant myocarditis” belongs to the field of disease diagnostic reagents and drugs. The biomarker comprises Siglec-5. The biomarkers combination is further selected from the group consisting of sST2, PAI-1, Siglec-5, CD163, CD40, P-Cadherin, CD14, CTLA4. The invention finds that the levels of the biomarker in plasma of patients with fulminant myocarditis is increased, and proves that the biomarker plays a role in diagnosing fulminant myocarditis and a role as a drug target in relieving and/or improving fulminant myocarditis. The level of the biomarker can be detected to forecast or auxiliary diagnose fulminant myocarditis or estimate prognosis of fulminant myocarditis. Meanwhile, level of the biomarkers is controlled through drugs, more intensified diagnosis and follow-up treatment can be carried out on diseases, and the biomarkers have huge clinical application value.

Abstract: Embodiment provides a semiconductor structure and a fabrication method thereof, and relates to the field of semiconductor technology. The method includes: providing a substrate having an array region including a first region and a second region arranged adjacently; and forming a first memory in the first region and forming a second memory in the second region by means of a same fabrication process, the fabrication process being a process configured for fabricating the first memory.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The fabricating method includes: providing a substrate including an array region and a peripheral region; and forming, on the substrate, a first mask layer covering the array region and the peripheral region, the first mask layer having a first device structure pattern directly facing the array region and a second device structure pattern directly facing the peripheral region. Through the method for fabricating a semiconductor structure, the first mask layer having the first device structure pattern and the second device structure pattern is formed on the substrate, and then the substrate is etched by using the first device structure pattern and the second device structure pattern as mask layer to synchronously form a peripheral region structure and an array region structure on the substrate.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure includes: providing a substrate including an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate; forming a first device structure pattern on the first mask layer, and then forming a second device structure pattern on the first mask layer; and etching the substrate by using the first device structure pattern and the second device structure pattern as mask layer to form a peripheral region structure and an array region structure synchronously on the substrate. Technological processes are simplified, fabrication difficulties are reduced, and production efficiency is improved.

Abstract: Embodiment provides a semiconductor structure and a fabrication method thereof, and relates to the field of semiconductor technology. The fabrication method includes providing a substrate including a peripheral circuit region and an array region having a memory cell, where the peripheral circuit region includes a first region and a second region. In the present disclosure, a logic device configured to control the memory cell and a magnetic memory device are simultaneously fabricated in the peripheral circuit region by means of a process for fabricating a dynamic random access memory (DRAM), such that the same semiconductor structure has two types of memory structures at the same time. Compared with a technology for fabricating two types of memory structures separately, fabricating steps can be simplified, and fabricating costs can be reduced.

Abstract: Embodiments provide a layout and a processing method thereof, a storage medium and a program product. The layout has a first memory area and a second memory area. The layout includes a base substrate array pattern and a storage pattern, the base substrate array pattern includes a plurality of plug patterns spaced apart; and the storage pattern includes a magnetic tunnel junction pattern in the first memory area and a capacitor pattern in the second memory area. The magnetic tunnel junction pattern shares a partially overlapped area with a given one of the plurality of plug patterns in the first memory area, and the capacitor pattern shares a partially overlapped area with a given one of the plurality of plug patterns in the second memory area.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate including a first array region and a second array region. The first array region is provided with a first memory array comprising a plurality of first memory structures, and the second array region is provided with a second memory array comprising a plurality of second memory structures. Compared with related technologies where different memory structures are stacked on a substrate, in this embodiment, the plurality of first memory structures and the plurality of second memory structures are arranged side by side on the substrate, which is advantageous to simplifying fabrication processes and improving production efficiency.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.

Abstract: The present disclosure relates to an OLED display substrate, including: a base substrate; a light emitting structure layer, and a light extraction structure . The light extraction structure includes a plurality of light extraction layers corresponding to the plurality of sub-pixels one-to-one; the orthographic projection of each of light extraction layers on the base substrate covers a corresponding sub-pixel, and the thicknesses of the light extraction layers corresponding to the sub-pixels of the same color are the same. The plurality of light extraction layers at least includes a first light extraction layer corresponding to a first sub-pixel of a first color, and the thickness of the first light extraction layer is different from the thickness of the light extraction layers corresponding to the sub-pixels of other colors, so that the OLED display substrate renders preset colors under preset viewing angles.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.