Abstract: Described is an apparatus comprising a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may be an elastic buffer coupled to a received clock, a local clock, a received-clock data, and a local-clock data. The second circuitry may assert a first flag when a set of values on the received-clock data matches part of a skip ordered set. The third circuitry may assert a second flag when a set of values on the local-clock data matches part of the skip ordered set. The fourth circuitry may increment a count value upon assertion of the first flag and may stop incrementing the count value upon assertion of the second flag. In some embodiments, additional circuitries may extract a first timestamp from a packet, sum the first timestamp and the count value, and substitute the sum for the first timestamp within the packet.

Abstract: A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

Abstract: An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.

Abstract: Described is an apparatus comprising a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may be an elastic buffer coupled to a received clock, a local clock, a received-clock data, and a local-clock data. The second circuitry may assert a first flag when a set of values on the received-clock data matches part of a skip ordered set. The third circuitry may assert a second flag when a set of values on the local-clock data matches part of the skip ordered set. The fourth circuitry may increment a count value upon assertion of the first flag and may stop incrementing the count value upon assertion of the second flag. In some embodiments, additional circuitries may extract a first timestamp from a packet, sum the first timestamp and the count value, and substitute the sum for the first timestamp within the packet.

Abstract: Techniques for reducing idle power consumption of a port are described herein. An example method includes determining device presence using a pull-down resistor disposed in a downstream port. The method also includes initiating a low power state of a link between the downstream port and an upstream device. The method also includes disabling the pull-down resistor in response to initiating the low power state.

Abstract: A source component includes a clock source to generate a clock signal, a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect, and a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits. The clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane and a second clock pulse of the clock signal on a second data lane. A sink component is to recover the first clock pulse of the clock signal from the first data lane and the second clock pulse of the clock signal from the second data lane, wherein the clock recovery circuit includes clock reconstruction logic to reconstruct the clock signal from the first clock pulse and the second clock pulse.

Abstract: A source component includes a clock source to generate a clock signal, a plurality of front-end driver circuits to transmit signals to a sink component over a plurality of data lanes of an interconnect, and a clock distribution circuit coupled to the clock source and the plurality of front-end driver circuits. The clock distribution circuit is to distribute a first clock pulse of the clock signal on a first data lane and a second clock pulse of the clock signal on a second data lane. A sink component is to recover the first clock pulse of the clock signal from the first data lane and the second clock pulse of the clock signal from the second data lane, wherein the clock recovery circuit includes clock reconstruction logic to reconstruct the clock signal from the first clock pulse and the second clock pulse.

Abstract: Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer that are compatible with a standard USB2 protocol. The link layer and protocol layer to control a physical layer for transmitting and receiving data on a pair of signal lines. The physical layer includes a fully-digital Low-Speed/Full-Speed (LS/FS) transceiver to transmit and receive data on the pair signal lines using single-ended digital communications on the pair of signal lines.

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract: A system and method of conducting precision time management in a universal serial bus system with a retimer. The method includes initiating, from the retimer, a link delay management request on an upstream-facing port of the retimer. The method further includes receiving, at a downstream-facing port of the retimer, a link delay management request and responding to the request received on the downstream-facing port.

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

Abstract: An apparatus for retimer configuration and control is described herein. The apparatus includes at least one retimer. The is to receive an inband low frequency periodic signal (LFPS), and to send an inband LFPS based pulse width modulation message (LBPM) in response to the inband LFPS. The retimer is configured by decoding the LBPM.

Abstract: Embodiments of a multi-transceiver wireless communication device and methods for adaptive multi-band communication are generally described herein. In some embodiments, the multi-transceiver wireless communication device is configurable for half-duplex operation and for asymmetrical full-duplex operation on two non-interfering channels. In some embodiments, a contention-based channel access procedure may be performed to attempt to gain access to both a primary channel and an auxiliary channel. A primary transceiver and an auxiliary transceiver may be configured for asymmetrical full-duplex operation when access to both the primary channel and the auxiliary channel is granted. One of the transceivers may be configured for half-duplex operation when access to only one of the channels is granted.

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

Abstract: An apparatus for retimer configuration and control is described herein. The apparatus includes at least one retimer. The is to receive an inband low frequency periodic signal (LFPS), and to send an inband LFPS based pulse width modulation message (LBPM) in response to the inband LFPS. The retimer is configured by decoding the LBPM.

Abstract: A method and system for communicating data between two devices are described herein. The method detects an electrical signal of a first protocol from a first device in a repeater, wherein the first protocol comprises single-ended signaling. The method also determines the speed of the electrical signal. Additionally, the method converts the electrical signal of the first protocol into an electrical signal of a second protocol based on the speed of the electrical signal. The second protocol comprises differential signaling. Furthermore, the method sends the electrical signal of the second protocol to a second device. In addition, the method stops the electrical signal of the second protocol to the second device when the electrical signal of the second protocol indicates an end of data flow.

Abstract: Systems and methods for operating a universal serial bus are described herein. The method includes sending packet data from a USB2 device to a USB2 host on a pair of signal lines, and after sending the packet data, sending an End-Of-Packet (EOP) signal from the USB2 device to the USB2 host. The method also includes, entering the USB2 device into idle state after sending the EOP signal. The method also includes sending a digital ping from the USB2 device to the USB2 host to indicate device presence during idle state.

Abstract: The present invention provides a device (1) for assisting a cough comprising a hosing (3), a chamber (5) formed in the housing, a mouthpiece (7) communicating with the chamber and exposed out of the housing, and an electromagnetic valve (9) assembly for opening or closing the chamber at a pre-set frequency. The device for assisting a cough according to the present invention may produce a high cough pressure and thus form a strong cough airflow to loose and cough the lung mucus out of the airways, and may prevent the collapse of the patient's airway caused by the rapid release of the cough pressure.