Abstract: A semiconductor memory device divides a clock signal to generate a first clock signal and a second clock signal, outputs a chip selection signal as a first chip selection signal in response to the first clock signal, outputs the buffered chip selection signal as a second chip selection signal in response to the second clock signal, outputs the first chip selection signal as a third chip selection signal in response to the second clock signal, outputs a buffered command and address as a first command and address in response to the first clock signal, outputs the buffered command and address as a second command and address in response to the second clock signal, outputs the first chip selection signal as a first selection signal in response to the first clock signal, and outputs the third chip selection signal as a second selection signal in response to the second clock signal.

Abstract: A semiconductor memory device divides a clock signal to generate a first clock signal and a second clock signal, outputs a chip selection signal as a first chip selection signal in response to the first clock signal, outputs the buffered chip selection signal as a second chip selection signal in response to the second clock signal, outputs the first chip selection signal as a third chip selection signal in response to the second clock signal, outputs a buffered command and address as a first command and address in response to the first clock signal, outputs the buffered command and address as a second command and address in response to the second clock signal, outputs the first chip selection signal as a first selection signal in response to the first clock signal, and outputs the third chip selection signal as a second selection signal in response to the second clock signal.

Abstract: A memory device includes a delay locked loop that generates a first code for delaying a reference clock in a first operation mode that is a normal operation mode, generates a second code for delaying the reference clock in a second operation mode that is a refresh mode, and delays the reference clock in response to one of the first and second codes depending on one of the first and second operation modes, and a data output circuit that outputs a data strobe signal (DQS) using the delayed reference clock.

Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

Abstract: A memory device may be configured to receive a differential data strobe signal and an external data signal from outside the memory device, the memory device may include control circuitry configured to, extract a common mode of the differential data strobe signal to generate a common mode signal, generate an internal data signal based on the external data signal and the common mode signal, and generate an internal data strobe signal based on the differential data strobe signal, the internal data strobe signal associated with latching the internal data signal.

Abstract: A memory device and method of operation for latency control in which a source clock signal having a first frequency is divided to provide a divided clock signal having a second frequency that is less than the first frequency as an input to a delay-locked loop circuit in an initialization mode. A locking operation may be performed to align the divided clock signal and a feedback clock signal that is generated by delaying the divided clock signal through the delay-locked loop circuit. A loop delay of the delay-locked loop circuit is measured after the locking operation is completed. The latency control is performed efficiently by measuring the loop delay using the divided clock signal in the initialization mode.

Abstract: An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.

Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.

Abstract: A memory device configured to perform a ZQ calibration method may include a first die and a second die that share a resistor connected to a ZQ pin. The first die may be configured to perform a first calibration operation using the resistor in response to a ZQ calibration command applied from outside of the memory device. The first die may be configured to generate a ZQ flag signal after the first calibration operation ends and perform a second calibration operation. The second die may be configured to perform the first calibration operation in response to the ZQ flag signal and perform a second calibration after the first calibration operation of the second die ends.

Abstract: A memory device includes a main driver and a pre-driver. The main driver provides an output signal to a host based on a plurality of driving signals. The pre-driver provides the main driver with the plurality of driving signals in order to calibrate a slew rate of the output signal based on an output resistance value of the main driver and a resistance value of an on-die termination circuit of the host. The pre-driver is configured to generate a first driving signal of the plurality of driving signals in response to an input signal regardless of a control signal, and to generate a second driving signal of the plurality of driving signals in response to the input signal and the control signal.

Abstract: A memory device includes a first on-die termination circuit, a second on-die termination circuit, a voltage generator, and a code generator. The first on-die termination circuit may correspond to a data input buffer. The second on-die termination circuit may correspond to a command/address buffer. The voltage generator may generate a reference voltage. The code generator may generate a resistance calibration code of a selected one of the on-die termination circuits in response to the reference voltage. The reference calibration code may calibrate a resistance value of the selected on-die termination circuit.

Abstract: A memory device including a command window generator is provided. The command window generator is configured to generate a delay signal by converting a delay time between a clock signal input to a write path circuit and a clock signal output to a write path replica circuit into a number of cycles of an internal clock signal, by using the write path circuit and the write path replica circuit, and generate a command window to correspond to a data window using the delay signal. The delay window may correspond to a burst length of write data.

Abstract: An output buffer circuit may include a pulse generator, a transmitter, and an emphasis controller. The pulse generator generates a pulse signal for determining an emphasis execution period. The transmitter may receive an input data and to have a first output resistance value, which is determined by the input data and a resistance calibration code, and to have a second output resistance value different from the first output resistance value, which is determined by the input data and an emphasis code different from the resistance calibration code for executing an emphasis operation during the emphasis execution period, based on the pulse signal. The emphasis controller provides the resistance calibration code or the emphasis code to the transmitter based on the pulse signal. The emphasis code may include a first code determined by the input data regardless of the resistance calibration code.

Abstract: A memory device configured to perform a ZQ calibration method may include a first die and a second die that share a resistor connected to a ZQ pin. The first die may be configured to perform a first calibration operation using the resistor in response to a ZQ calibration command applied from outside of the memory device. The first die may be configured to generate a ZQ flag signal after the first calibration operation ends and perform a second calibration operation. The second die may be configured to perform the first calibration operation in response to the ZQ flag signal and perform a second calibration after the first calibration operation of the second die ends.

Abstract: A memory module includes a first memory device including a first one-die termination circuit for impedance matching of a signal path and a second memory device sharing the signal path with the first memory device and including a second on-die termination circuit for impedance matching of the signal path, wherein the signal path corresponds to a command or address signal path provided from a host, and the first and second on-die termination circuits are individually controlled according to control of the host.

Abstract: A memory device includes a main driver and a pre-driver. The main driver provides an output signal to a host based on a plurality of driving signals. The pre-driver provides the main driver with the plurality of driving signals in order to calibrate a slew rate of the output signal based on an output resistance value of the main driver and a resistance value of an on-die termination circuit of the host. The pre-driver is configured to generate a first driving signal of the plurality of driving signals in response to an input signal regardless of a control signal, and to generate a second driving signal of the plurality of driving signals in response to the input signal and the control signal.

Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

Abstract: An output buffer circuit may include a pulse generator, a transmitter, and an emphasis controller. The pulse generator generates a pulse signal for determining an emphasis execution period. The transmitter may receive an input data and to have a first output resistance value, which is determined by the input data and a resistance calibration code, and to have a second output resistance value different from the first output resistance value, which is determined by the input data and an emphasis code different from the resistance calibration code for executing an emphasis operation during the emphasis execution period, based on the pulse signal. The emphasis controller provides the resistance calibration code or the emphasis code to the transmitter based on the pulse signal. The emphasis code may include a first code determined by the input data regardless of the resistance calibration code.

Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.

Abstract: A memory device including a command window generator is provided. The command window generator is configured to generate a delay signal by converting a delay time between a clock signal input to a write path circuit and a clock signal output to a write path replica circuit into a number of cycles of an internal clock signal, by using the write path circuit and the write path replica circuit, and generate a command window to correspond to a data window using the delay signal. The delay window may correspond to a burst length of write data.