Abstract: Methods and apparatus to determine nearfield localization using phase and received signal strength indication (RSSI) diversity are disclosed. An example method includes determining a first strength of an electric field and a second strength of a magnetic field, the electric field and the magnetic field associated with an electromagnetic signal sent from a transmitter; determining a difference between the first strength and the second strength; and determining a transmitter distance based on the difference between the first strength and the second strength.

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract: An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment.

Abstract: A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).

Abstract: An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment.

Abstract: An innovative software-defined backchannel communication scheme is provided for use in ultra-low power devices. The technique enables interconnecting heterogeneous devices through a WiFi backchannel that can be realized with existing infrastructure without any hardware modifications. The backchannel communication scheme can also be extended to other OFDM based communication systems, such as cellular 4G LTE.

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract: An apparatus for preventing a relay attack that includes a microcontroller, a receiver, and a transmitter. The receiver is configured to receive a challenge message from a verifier. The challenge message has a challenge message frequency at a first challenge message frequency during a first time slot. The transmitter is configured to transmit a response message to the verifier. The response message has a response message frequency at a first response message frequency during the first time slot. The first response message frequency is different than the first challenge message frequency. The challenge message frequency is at a second challenge message frequency and the response message frequency is at a second response message frequency during a second time slit. The second challenge message frequency is different than the second response message frequency.

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

Abstract: An embodiment of the invention includes an Openflow switch. The Openflow switch includes Openflow ALL groups. The Openflow ALL groups include ALL group buckets. During ingress ALL group buckets are represented in ingress as a list of output ports with associated queue ID's and associated copy-counts. Each ALL group bucket is represented in egress by an egress Openflow table entry where the egress Openflow table entry matches a group ID and a bucket ID. An action entry in an ALL group bucket table entry is the set of actions in the Openflow ALL group bucket excluding an output port and queue assignment.

Abstract: A method for performing packet lookups is provided. Packets (which each have a body and a header) are received and parsed to parsing headers. A hash function is applied to each header, and each hashed header is compared with a plurality of binary rules stored within a primary table, where each binary rule is a binary version of at least one ternary rule from a first set of ternary rules. For each match failure with the plurality of rules, a secondary table is searched using the header associated with each match failure, where the secondary table includes a second set of ternary rules.

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, where the vector comprises data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations. The one or more actions comprise modifying the data values representing information for a packet. The block also comprises at least one stateful memory comprising stateful memory data values. The one or more actions includes various stateful actions for reading stateful memory, modifying data values representing information for a packet, as a function of the stateful memory data values; and storing modified stateful memory data value back into the stateful memory.

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

Abstract: Hashing complexity is reduced by exploiting a hashing matrix structure that permits a corresponding hashing function to be implemented such that an output vector of bits is produced in response to an input vector of bits without combining every bit in the input vector with every bit in any row of the hashing matrix.

Abstract: A computer program that is embodied on a storage medium for execution on a processor is provided. With this computer program, A current cost is calculated for each transition on a bus having a predetermined width for a functional circuit so as to form a transition cost matrix. Then, a predetermined number of the lowest cost transitions for from the transition cost matrix is determined so as to generate a probability transition matrix. The product of the probability transition matrix and the transition cost matrix can be iteratively determined, while also updating the probability transition matrix until the probability transition matrix converges.

Abstract: A computer program that is embodied on a storage medium for execution on a processor is provided. With this computer program, A current cost is calculated for each transition on a bus having a predetermined width for a functional circuit so as to form a transition cost matrix. Then, a predetermined number of the lowest cost transitions for from the transition cost matrix is determined so as to generate a probability transition matrix. The product of the probability transition matrix and the transition cost matrix can be iteratively determined, while also updating the probability transition matrix until the probability transition matrix converges.