Patents by Inventor Hun Wah Cheah

Hun Wah Cheah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941336
    Abstract: Circuit devices include a first chip that includes functional blocks. A second chip has routing circuitry that provides configurable signal communications between functional blocks of the first chip and configuration memory that controls the routing circuitry and that further controls operation of the functional blocks of the first chip.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 26, 2024
    Assignee: OPPSTAR TECHNOLOGY SDN BHD
    Inventors: Kim Pin Tan, Hun Wah Cheah
  • Publication number: 20230288953
    Abstract: Circuit devices, configurable circuit devices, and methods of configuring the same include a first logic block and a routing block. The routing block routes a clock signal to the first logic block and includes a selectable delay circuit with delay paths and a multiplexer that selects one of the delay paths. Each of the delay paths delays the clock signal by a different amount.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 14, 2023
    Inventors: Kim Pin Tan, Hun Wah Cheah
  • Publication number: 20230140876
    Abstract: Circuit devices include a first chip that includes functional blocks. A second chip has routing circuitry that provides configurable signal communications between functional blocks of the first chip and configuration memory that controls the routing circuitry and that further controls operation of the functional blocks of the first chip.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 11, 2023
    Inventors: Kim Pin Tan, Hun Wah Cheah
  • Publication number: 20230077881
    Abstract: Configurable circuits include an input selection region, a computation region, a switching region, and an output region. The input selection region includes a set of input multiplexers and selects and routes input signals. The computation region includes a set of lookup tables, each lookup table being coupled to selected signals from the input selection stage to generate a respective output signal. The switching region includes a set of output multiplexers, each output multiplexer being coupled to output signals from the set of lookup tables to provide circuit outputs responsive to respective output selection signals. The output region includes a domino logic stage, having a set of transistors, coupled to output signals from the set of lookup tables to provide circuit outputs that determine combinations of the signals output by the set of lookup tables.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Kim Pin Tan, Kok Keong Liaw, Hun Wah Cheah