Abstract: A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.

Abstract: Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.

Abstract: A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

Abstract: A single-stage level shifting circuit is used to interface control signals across the boundary between voltage domains with differing positive or ground voltage potentials Asserted states are determined by the difference between the positive voltages potentials and the ground potentials. A lower positive power supply potential is not used to turn OFF PFET coupled to a higher positive power supply potential. Likewise a higher ground power supply potential is not used to turn OF NFETs coupled to a power domain where is significant ground shift. The single stage level shifting circuit has keeper devices that hold asserted states using voltages within the power gated domain.

Abstract: A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

Abstract: An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.

Abstract: Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials of the power supply from circuitry with large high leakage devices. Driver circuits comprise a low leakage logic path for holding logic states of the output. A high leakage logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each high leakage path that enhances the current drive of a logic state on the output are leakage stress relieved by allowing their drive inputs to collapse after the output logic state has been asserted. The high leakage logic paths employ multiple stages with collapsing logic states that are generated in response to asserted logic states on the output and logic states of the low leakage logic path thus reducing the device sizes needed to control leakage.

Abstract: A phase detector employs a modified logic gate in conjunction with a set/reset latch to make a phase detector that generates control outputs for use in increasing and decreasing the delay in a delay circuit in the path of a feedback clock generated by delaying a reference clock. The delay circuit provides a controllable delay from less than to greater than one clock cycle of the reference clock. The phase detector generates an up control (UP) signal for increasing delay when the feedback clock leads the reference clock and a down control (DN) signal for decreasing delay when the feedback clock lags the reference clock. The UP signal and DN signal are updated each clock cycle when the leading clock edge makes a transition.

Abstract: CMOS circuitry is partitioned into first and second logic circuit domains. The first logic circuit domain may be optionally a cuttable domains (C_Domains) where circuitry has power supply gating to reduce leakage power and non-cuttable domains (NC_Domains) where circuitry does not have power supply gating. Each output that couples signals from one logic circuit domain to another logic circuit is interfaced with a C_driver and a S_keeper which automatically assure that the output state is held when circuitry is power-gated put to reduce leakage power. The S_keeper and C_driver have low leakage circuits that maintain signal states and are not used for high speed operation.

Abstract: An interleaved VCO is configured using a ring oscillator with voltage controlled feedforward inverting stages coupled around the inverting stages making up the basic ring oscillator to enable the frequency of the ring oscillator to be voltage controlled. The feedforward inverting stages comprise a complementary inverter stage and a voltage controlled transfer gate. Complementary control voltages are coupled to the gates of the complementary transfer gate FET devices. Likewise, the complementary control voltages are coupled to the corresponding body of the FET devices in the transfer gate and in the inverting stage. The complementary control voltages may also be connected to the body of the complementary FET devices in the inverting stages making up the basic ring oscillator. This allows the frequency range of the VCO to be extended without having to switch the feedforward paths into an out of the circuit.

Abstract: A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer may be an inverter, non-inverter, or provide a multiple input logic function.

Abstract: A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.

Abstract: A VCO is configured using a ring oscillator with voltage controlled feedforward inverting stages coupled around the inverting stages making up the basic ring oscillator to enable the frequency of the ring oscillator to be voltage controlled. A latch and multiplexer is used to select between two or more outputs within the ring oscillator to change the basic frequency range of the VCO glitch free. To achieve a wide range VCO, additional stages are added to the basic ring oscillator. When the number of stages is an odd number greater than seven, then the voltage controlled feedforward inverting stages feedback to the outputs of the first and second inverting stages of the ring oscillator. Two additional multiplexers are added to select which feedforward inverting stage is coupled to the first and second inverting stage. This allows a wide range interleaved VCO that switches between frequency ranges glitch free.

Abstract: A reference signal and a voltage controlled oscillator (VCO) output are compared for relative phase and frequency differences. A lead error signal is generated if the reference signal leads the VCO output and a lag error signal is generated if the reference signal lags the VCO output the lead and lag error may result from a combination for phase and frequency differences between the reference signal and the VCO output. A time window is used to sample the polarity of the lead and lag error signals by incrementing and decrementing a phase error signal. If the phase error signal reaches a threshold value within the time window, a Reset Delta pulse is generated and if the phase error signals does not reach the maximum delta value within the time window a Reset Total pulse is generated. A variable first gain signal is increased on each Reset Delta pulse and decreased on each Reset Total pulse and limited to a value between predetermined maximum and minimum values.

Abstract: An LSDL circuit has both an output and a complementary output generated by inverting the output with an inverter logic gate. A keeper PFET is added by coupling its drain terminal to the dynamic node. The keeper PFET has its source terminal coupled to the positive power supply voltage and its gate terminal coupled to the complementary output. The output and the dynamic node may both be at a logic one when the output is a logic one from the previous evaluation cycle and the dynamic node is precharged. In this case, the complementary output is a logic zero which turns ON the keeper PFET and reinforces the precharge on the dynamic node. When the output is evaluating to a logic zero, the output will transition quickly to a logic zero. If the output is transitioning from a logic zero to a logic one, then the keeper PFET is OFF and does not affect the dynamic node.

Abstract: A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k?1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k?1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k?1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k?1.

Abstract: An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.

Abstract: The N channel field effect transistor (NFET) of the inverting output stage of a LSDL gate is split into a large NFET and a small NFET. The large NFET is coupled to a feedforward pulse so that it is turned ON only when the inverting output is a logic one. When the inverting output is a logic one, another inverting stage turns ON if the dynamic node evaluates to a logic zero. The dynamic node is inverted and coupled to the large NFET on the inverting output stage thus quickly pulling the inverting output to a logic zero. The small NFET is turned ON as a keeper device through the normal logic path. If the inverting data output is a logic zero the feedforward pulse is not generated. By making the largest NFET a pulsed device the other FETs are reduced in size resulting in leakage and switching power savings.

Abstract: LSDL logic is provided with circuitry that has logic controls to provide two modes of operation. The half latch and the PFET that normally forms the keeper function on the dynamic node are modified. The inverter function of the series connected PFET and NFET have their corresponding positive and negative power supply terminals coupled to logic gates. In this way, the inverter may be turned ON so that the half latch functions as a keeper or it may be turned OFF to remove it from operating at all in the mode where the LSDL logic circuit needs to operate with a fast pulse clock. Likewise, the positive supply voltage may be removed while allowing the NFET device to operate to turn ON the PFET pull-up device for burn-in operation.

Abstract: Circuits within a logic domain use partitioned power supply buses. Selected of the power supply buses are coupled to the power supply voltage potentials with electronic switches with gradated conductivity and leakage current. When the circuits are actively switching during a logic operation, the power supply voltage potentials are coupled to the buses with maximum conductivity. At predetermined times later, selected of the electronic switches are switched OFF to reduce leakage current. Lower conductivity and thus lower leakage switches remain ON to ensure corresponding logic states are maintained during a controlled low leakage time period. Various logic configurations are used to switch OFF high leakage devices.