Patents by Inventor Hung Cheng

Hung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240186323
    Abstract: An integrated circuit includes a plurality of transistors and a vertical local interconnection. The transistors include a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side side of the integrated circuit than the back-side source/drain epitaxies. The vertical local interconnection connects a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies. A covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion.
    Type: Application
    Filed: January 20, 2023
    Publication date: June 6, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Yu LIN, Chun-Fu CHENG, Hsiang-Hung HUANG
  • Patent number: 12001026
    Abstract: A head-mounted display includes a display device, a connecting structure and a head abutting portion. The connecting structure is in a shape of strip. The connecting structure has two opposite ends. The ends are respectively connected with the display device. The connecting structure and the display device define an accommodation space. The accommodation space is configured to accommodate a head of a user. The head abutting portion is pivotally connected with the connecting structure. The head abutting portion is at least partially located between the connecting structure and the display device. The head abutting portion is configured to abut against the head of the user.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 4, 2024
    Assignee: Quanta Computer Inc.
    Inventors: Hung-Yu Lin, Chun-Feng Yeh, Jia-Cheng Chang, Bing-Kai Huang, Chun-Nan Huang, Chun-Lung Chen
  • Patent number: 12002813
    Abstract: A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hung Cheng, Ching I Li, Chia-Shiung Tsai
  • Patent number: 12002399
    Abstract: An image display method for handling a dynamic image signal including a plurality of continuous video frames, wherein the method includes steps as follows: Firstly, a first display parameter is output to display an Nth video frame of the plurality of continuous video frames according to a first attribute data of the Nth video frame. Then, at least one of (N+K)th video frame is detected, and when the at least one of the (N+K)th video frame has second attribute data, the first display parameter is output to display the at least one of the (N+K)th video frames. Subsequently, an (N+K+1)th video frame is detected, and when the (N+K+1)th video frame has the second attribute data, a second display parameter is output to display the (N+K+1)th video frame according to the second attribute data. Wherein, K is a positive integer greater than 1.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: June 4, 2024
    Assignee: BenQ Corporation
    Inventors: Hung-Chi Tsai, Chen-Cheng Huang
  • Publication number: 20240177449
    Abstract: A copy-protected image display system is provided to include an eyeglasses display device, and an image content server that stores a source image, and device information that corresponds to the eyeglasses display device. The image content server introduces a small data change into the source image based on the device information to obtain a first modified image, converts the first modified image into a second modified image based on an image modification rule, and transmits the second modified image to the eyeglasses display device through a data transceiving device. The eyeglasses display device converts the second modified image back to the first modified image, and displays the first modified image.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventor: Hung-Cheng Kuo
  • Publication number: 20240173819
    Abstract: A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.
    Type: Application
    Filed: September 12, 2023
    Publication date: May 30, 2024
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Chih-Chun Cheng, Wen-Nan Cheng, Meng-Bi Lin, Chi-Feng Li, Tzu-Fan Chiang, Wei-Jen Chen, Chien Hung Chen, Hsiu Chi Liang, Ying-Ru Shih
  • Patent number: 11997935
    Abstract: A resistive random-access memory (RRAM) device, including a bottom electrode, a high work function layer, a resistive material layer and a top electrode sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part, first spacers covering sidewalls of the top part and the top electrode, and second spacers covering sidewalls of the bottom part, thereby constituting a RRAM cell.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: May 28, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Hung Yu, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11995471
    Abstract: A resource integration method includes the following steps: a receiving module receives access information from a guest operating system on the host device; the access information is used to determine whether the frame rate is lower than a frame rate threshold; when the receiving module determines that the frame rate is lower than the frame rate threshold, the receiving module transmits an external resource request signal to the receiving module; after the receiving module receives the external resource request signal, a resource management module (which is located in the bridge module) selects an optimal external device from a specific category (among a plurality of categories in a candidate list), and a calculation operation or a storage operation corresponding to the specific category is transmitted to the optimal external device for calculation or storage by the bridge module.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: May 28, 2024
    Assignee: ACER INCORPORATED
    Inventors: Kuan-Ju Chen, Wen-Cheng Hsu, Hung-Ming Chang, Chih-Wen Huang, Chao-Kuang Yang
  • Patent number: 11996165
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 28, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
  • Patent number: 11996361
    Abstract: A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Cheng Chin, Yao-Min Liu, Hung-Wen Su, Chih-Chien Chi, Chi-Feng Lin
  • Patent number: 11989046
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Patent number: 11990440
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chang-Jung Hsueh, Kai-Jun Zhan, Yung-Sheng Lin
  • Patent number: 11990375
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
  • Publication number: 20240157063
    Abstract: A drug delivery device including a main housing and a drug delivery module is provided. The main housing has an internal space. The drug delivery module is disposed in the internal space so as to be isolated from an external environment. The drug delivery module includes a drug bottle that contains a liquid drug and a driver that is connected to the drug bottle. The driver is configured to push the liquid drug to pass through a drug nebulization structure of the drug bottle such that the liquid drug is nebulized into a nebulized drug.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Inventors: Chieh-Sheng Cheng, JUI-SHUI CHEN, YI-HUNG WANG
  • Publication number: 20240162333
    Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20240162349
    Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
  • Publication number: 20240159105
    Abstract: A motorized blind and a manual switching clutch structure thereof are disclosed. The motorized blind includes a blind assembly, a spring power module, an electric motor module and the manual switching clutch structure. The blind assembly includes a bottom rail which can be driven by the spring power module to move. The manual switching clutch structure is disposed between the spring power module and the electric motor module. By rotating a knob of the manual switching clutch structure, the motorized blind can be switched between a motor driving mode in which the electric motor module participates in the movement of the bottom rail by driving the spring power module, and a manual driving mode in which the spring power module individually participates in the movement of the bottom rail.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 16, 2024
    Applicant: Nien Made Enterprise Co., Ltd.
    Inventors: Chao-Hung Nien, Chin-Chu Chiu, Hui-Ping Cheng
  • Patent number: 11984485
    Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh
  • Patent number: 11984649
    Abstract: A wearable device includes a conducting frame, a circuit board, and a grounding member. The conducting frame includes a first part and a second part that are separated. The circuit board has a system grounding surface and is disposed inside the conducting frame. The grounding member is disposed inside the conducting frame and connected to the first part. The first part and the grounding member are formed as a first antenna. The first part has a first feeding terminal. The grounding member has a first grounding terminal, and the first grounding terminal is connected to the system grounding surface of the circuit board. The second part is formed as a second antenna. The second antenna has a second feeding terminal, a second grounding terminal, and a third grounding terminal. The second and the third grounding terminals are connected to the system grounding surface of the circuit board.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: May 14, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Kuo-Chi Cheng, Po-Yen Lai, Ping-Hung Lu
  • Patent number: 11980920
    Abstract: Embodiments of the present disclosure relate to apparatus and methods for cleaning an exhaust path of a semiconductor process tool. One embodiment provides an exhaust pipe section and a pipe cleaning assembly connected between a semiconductor process tool and a factory exhaust. The pipe cleaning assembly includes a residue remover disposed in the exhaust pipe section. The residue remover is operable to move in the exhaust pipe section to dislodge accumulated materials from an inner surface of the exhaust pipe section.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Chang Cheng, Cheng-Kuang Chen, Chi-Hung Liao