Patents by Inventor Hung-Cheng Chen
Hung-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989046Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.Type: GrantFiled: February 6, 2023Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
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Publication number: 20240162349Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.Type: ApplicationFiled: January 24, 2024Publication date: May 16, 2024Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
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Publication number: 20240144467Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.Type: ApplicationFiled: January 8, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
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Publication number: 20240145436Abstract: Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.Type: ApplicationFiled: December 29, 2023Publication date: May 2, 2024Inventors: Hung Cheng Chen, Yu Chun Chen, Hsuan Chao Hou
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Patent number: 11963295Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.Type: GrantFiled: January 27, 2022Date of Patent: April 16, 2024Assignee: Industrial Technology Research InstituteInventors: Hung-Hsien Ko, Yi-Cheng Lu, Heng-Yin Chen, Hao-Wei Yu, Te-Hsun Lin
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Package structure comprising buffer layer for reducing thermal stress and method of forming the same
Patent number: 11961777Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: GrantFiled: June 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Publication number: 20240102154Abstract: A vacuum processing apparatus (110) for deposition of a material on a substrate is provided. The vacuum processing apparatus (110) includes a vacuum chamber comprising a processing area (111); a deposition apparatus (112) within the processing area (111) of the vacuum chamber; a cooling surface (113) inside the vacuum chamber; and one or more movable shields (220) between the cooling surface (113) and the processing area (111).Type: ApplicationFiled: February 24, 2020Publication date: March 28, 2024Inventors: Chun Cheng CHEN, Hung-Wen CHANG, Shin-Hung LIN, Chi-Chang YANG, Christoph MUNDORF, Thomas GEBELE, Jürgen GRILLMAYER
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Patent number: 11942543Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.Type: GrantFiled: June 29, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
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Patent number: 11923425Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.Type: GrantFiled: February 17, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Cheng Chiu, Tian Sheng Lin, Hung-Chou Lin, Yi-Min Chen, Chiu-Hua Chung
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Patent number: 11916146Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.Type: GrantFiled: April 11, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chiang Wu, Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen
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Patent number: 11862607Abstract: Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.Type: GrantFiled: August 16, 2021Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Hung Cheng Chen, Yu Chun Chen, Hsuan Chao Hou
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Patent number: 11649543Abstract: A sputtering target structure includes a body having a first side and an opposing second side. A first sputtering target is coupled to the first side of the body. The first sputtering target includes a first material. A second sputtering target is coupled to the second side of the body. The second sputtering target includes a second material. A rotation mechanism is coupled to the body and is configured to allow rotation of the body from a first orientation to a second orientation.Type: GrantFiled: February 8, 2022Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Yuan Chen, Hung-Cheng Chen, Chih-Hsuan Hsieh, Yu-Hsuan Wang
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Patent number: 11612050Abstract: A heat dissipation device includes a heat conductor. The heat conductor includes a heat dissipation side and a heat absorption side opposite to each other. The heat absorption side is formed by at least two contact planes. The at least two contact planes are arranged in parallel to each other, and a height difference exists between the at least two contact planes.Type: GrantFiled: December 7, 2020Date of Patent: March 21, 2023Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.Inventors: Hung-Cheng Chen, Tse-Hsien Liao
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Publication number: 20230047231Abstract: Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.Type: ApplicationFiled: August 16, 2021Publication date: February 16, 2023Inventors: Hung Cheng Chen, Yu Chun Chen, Hsuan Chao Hou
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Patent number: 11426793Abstract: A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.Type: GrantFiled: December 3, 2018Date of Patent: August 30, 2022Assignee: National Cheng Kung UniversityInventors: In-Gann Chen, Hung-Cheng Chen, Chia-Ming Yang, Steve Lien-Chung Hsu, Chang-Shu Kuo
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Publication number: 20220162744Abstract: A sputtering target structure includes a body having a first side and an opposing second side. A first sputtering target is coupled to the first side of the body. The first sputtering target includes a first material. A second sputtering target is coupled to the second side of the body. The second sputtering target includes a second material. A rotation mechanism is coupled to the body and is configured to allow rotation of the body from a first orientation to a second orientation.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Applicant: Taiwa Semiconductor Manufacturing Co, Ltd.Inventors: Ping-Yuan CHEN, Hung-Cheng CHEN, Chih-Hsuan HSIEH, Yu-Hsuan WANG
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Patent number: 11268186Abstract: A sputtering target structure includes a body having a first side and an opposing second side. A first sputtering target is coupled to the first side of the body. The first sputtering target includes a first material. A second sputtering target is coupled to the second side of the body. The second sputtering target includes a second material. A rotation mechanism is coupled to the body and is configured to allow rotation of the body from a first orientation to a second orientation.Type: GrantFiled: July 17, 2020Date of Patent: March 8, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Yuan Chen, Hung-Cheng Chen, Chih-Hsuan Hsieh, Yu-Hsuan Wang
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Patent number: 11262914Abstract: A solid-state drive and a performance optimization method for the solid-state drive are provided. The performance optimization method for the solid-state drive includes the following steps: detecting a queue depth of the solid-state drive to determine a use proportion of the queue depth; determining whether an access speed of the solid-state drive is raisable when the use proportion of the queue depth is higher than a first threshold proportion, so as to raise the access speed of the solid-state drive; and determining whether the access speed of the solid-state drive is reduceable when the use proportion of the queue depth is lower than a second threshold proportion, so as to reduce the access speed of the solid-state drive.Type: GrantFiled: April 29, 2020Date of Patent: March 1, 2022Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.Inventors: Hung-Cheng Chen, Tse-Hsien Liao
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Patent number: 11226863Abstract: A solid-state disk and a startup method are provided. The solid-state disk includes a control circuit, a firmware switching circuit, a first firmware storage unit, and a second firmware storage unit. The firmware switching circuit is coupled to the control circuit. The first firmware storage unit is coupled to the firmware switching circuit and stores a first firmware. The second firmware storage unit is coupled to the firmware switching circuit and stores a second firmware. The control circuit reads the first firmware storage unit or the second firmware storage unit according to whether the firmware switching circuit is triggered so as to startup according to the first firmware or the second firmware.Type: GrantFiled: December 13, 2020Date of Patent: January 18, 2022Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.Inventors: Hung-Cheng Chen, Tse-Hsien Liao
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Patent number: 11216649Abstract: A display device capable of automatically adjusting displayed image comprises a display device, a camera assembly, an image recognition device and a signal processor. The display device including a shell and a display panel partially exposed from the shell, wherein the display panel faces a first direction. The camera assembly obtains a first image with a first visual angle and obtain a second image with a second visual angle. The image recognition device generates a first instruction when the first image meets a first condition and generates a second instruction when the second image meets a second condition. The signal processor adjusts the display signal to conceal the displayed image according to the first instruction and to adjust the display signal to generate a reminder message on the displayed image according to the second instruction.Type: GrantFiled: April 20, 2020Date of Patent: January 4, 2022Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.Inventors: Hung-Cheng Chen, Tse-Hsine Liao, Chin Hui Chen, Chih-Hua Ke