Abstract: An optical detection device includes a first linear light source, a second linear light source, an optical sensor array and a processor. The first linear light source is adapted to project a first long strip illumination beam onto the target container. The second linear light source is adapted to project a second long strip illumination beam onto the target container, and the second long strip illumination beam is crossed with the first long strip illumination beam. The optical sensor array is adapted to receive a first long strip detection beam and a second long strip detection beam reflected from the target container. The processor is electrically connected to the optical sensor array. The processor is adapted to analyze intensity distribution of the first long strip detection beam and the second long strip detection beam to acquire a relative distance between the optical sensor array and the target container.

Abstract: Audio processing systems, such as full duplex digital telephone systems, are provided in which analog automatic level control (ALC) circuitry is employed to automatically control and stabilize the microphone output audio signal levels to a constant level for optimal digital signal processing. For example, an audio communication device (10) includes a microphone (11) to generate an audio signal, an analog automatic level control (ALC) circuit (13), coupled to an output of the microphone (11), to control a level of the audio signal output from the microphone (11) and output a level-controlled audio signal, and a DSP (digital signal processing) circuit (14) to process the level-controlled audio signal output from the ALC circuit (13). The ALC (13) allows audio signals to be captured by the microphone (11) with wide dynamic range, while stabilizing the microphone output level within a reduced dynamic range compatible with the limited dynamic range of the DSP circuitry (14) for enhanced performance.

Abstract: A digital signal processing apparatus comprises a main memory, a processing unit, a cache, and a rotate buffer unit. The main memory includes at least R memory banks for storing a plurality of data of digital signal. The cache is coupled between the main memory and the processing unit. The cache includes at least R×R cache units for storing part of data of the main memory to provide to the processing unit. The cache also temporarily stores operation results of the processing unit. The rotate buffer unit is coupled between the main memory and the cache for buffering and rotating the data outputted from each of the memory banks to write to the cache, and the data outputted from part of the cache units to write back to the corresponding memory banks respectively.

Abstract: Audio processing systems, such as full duplex digital telephone systems, are provided in which analog automatic level control (ALC) circuitry is employed to automatically control and stabilize the microphone output audio signal levels to a constant level for optimal digital signal processing. For example, an audio communication device (10) includes a microphone (11) to generate an audio signal, an analog automatic level control (ALC) circuit (13), coupled to an output of the microphone (11), to control a level of the audio signal output from the microphone (11) and output a level-controlled audio signal, and a DSP (digital signal processing) circuit (14) to process the level-controlled audio signal output from the ALC circuit (13). The ALC (13) allows audio signals to be captured by the microphone (11) with wide dynamic range, while stabilizing the microphone output level within a reduced dynamic range compatible with the limited dynamic range of the DSP circuitry (14) for enhanced performance.

Abstract: This invention provides a diversity receiver, which has N branches for receiving M versions of an input signal. The diversity receiver comprises N channel state information estimators, a demodulator and a combining and demapping device. After receiving the M versions of the input signal, the demodulator performs demodulation and then generates M demodulated signals. N channel state information estimators, one channel state information estimator equipped for each branch, respectively fetches the signals from the demodulator to generate M channel parameters related to the M versions of the input signal. The combining and demapping device receives the M demodulated signals, performs signal combining operations and symbol demapping, and finally generate a pre-correcting signal.

Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).

Abstract: The present invention relates to a re-configurable Viterbi decoder. By re-setting the values of some registers, the inside control path and data path of the Viterbi decoder can be appropriately changed so as to meet the requirements of different communication systems. The Viterbi decoder comprises a branch metric calculator for receiving data items to be decoded and calculating the branch metrics; an add-compare-select unit for performing an add-compare-select operation on the output of the branch metric calculator and the corresponding path metric; a path metric storage unit (PMS unit) for saving a new path metric produced by the add-compare-select operation in an in-place way; a path memory for storing the shifted out selection bit after the add-compare-select operation; and a trace back unit for reading the selection bit of the path memory so as to perform the feedback decoding.

Abstract: A digital signal processing apparatus comprises a main memory, a processing unit, a cache, and a rotate buffer unit. The main memory includes at least R memory banks for storing a plurality of data of digital signal. The cache is coupled between the main memory and the processing unit. The cache includes at least R×R cache units for storing part of data of the main memory to provide to the processing unit. The cache also temporarily stores operation results of the processing unit. The rotate buffer unit is coupled between the main memory and the cache for buffering and rotating the data outputted from each of the memory banks to write to the cache, and the data outputted from part of the cache units to write back to the corresponding memory banks respectively.

Abstract: This invention provides a diversity receiver, which has N branches for receiving M versions of an input signal. The diversity receiver comprises N channel state information estimators, a demodulator and a combining and demapping device. After receiving the M versions of the input signal, the demodulator performs demodulation and then generates M demodulated signals. N channel state information estimators, one channel state information estimator equipped for each branch, respectively fetches the signals from the demodulator to generate M channel parameters related to the M versions of the input signal. The combining and demapping device receives the M demodulated signals, performs signal combining operations and symbol demapping, and finally generate a pre-correcting signal.

Abstract: An analog cordless telephone has a handset and a base. The handset and/or the base of the telephone may include the following components. A phase locked loop (PLL) and a voltage controlled oscillator (VCO), adapted to be shared between a receive path and a transmit path. A first analog gate is adapted to gate a received audio signal on and off, in response to a clock signal. A second analog gate is adapted to gate a transmit audio signal on and off, in response to an inverted version of the clock signal. The transmit audio signal is enabled when the received audio signal is gated off, and the VCO is further adapted to be modulated by the enabled transmit audio signal to output a modulated RF signal.

Abstract: A digital signal processor structure by performing length-scalable Fast Fourier Transformation (FFT) discloses a single processor element (single PE), and a simple and effective address generator are used to achieve length-scalable, high performance, and low power consumption in split-radix-2/4 FFT or IFFT module. In order to meet different communication standards, the digital signal processor structure has run-time configuration to perform for different length requirements. Moreover, its execution time can fit the standards of Fast Fourier Transformation (FFT) or Inverse Fast Fourier Transformation (IFFT).

Abstract: A circuit for controlling processing of audio data and command data in a digital cordless telephone receiver includes a digital audio data path for processing digital audio information received; and a command data path for controlling the digital audio data path responsive to receiving command data.

Abstract: An analog cordless telephone has a handset and a base. The handset and/or the base of the telephone may include the following components. A phase locked loop (PLL) and a voltage controlled oscillator (VCO), adapted to be shared between a receive path and a transmit path. A first analog gate is adapted to gate a received audio signal on and off, in response to a clock signal. A second analog gate is adapted to gate a transmit audio signal on and off, in response to an inverted version of the clock signal. The transmit audio signal is enabled when the received audio signal is gated off, and the VCO is further adapted to be modulated by the enabled transmit audio signal to output a modulated RF signal.

Abstract: A method of simultaneously communicating voice and data on the same channel in an analog cordless telephone system involves generating an analog signal from an audible voice signal during a cordless telephone call; generating a frequency shift keying (FSK) signal from digital data having a nominal frequency of about 20 KHz; summing the analog signal and the FSK signal to produce a composite analog and digital signal; modulating a radio frequency (RF) carrier with the composite analog and digital signal to produce a modulated RF carrier; and transmitting the modulated RF carrier.

Abstract: A cordless telephone system divides the 25 channel bandwidth allocated by the Federal Communications Commission (FCC) into two bands in order to obtain improved noise performance. The front end is tuned to the center frequency of each band and the tuning of the receiver to specific channel frequencies is accomplished via a PLL.