Abstract: A method performed by a UE for repetition transmissions is provided. The method includes receiving DCI scheduling an uplink transmission; identifying a DCI format of the DCI; selecting, from a plurality of sets of preconfigured values, a set of preconfigured values that is mapped to the DCI format; and determining a number of times the uplink transmission is required to be repeated from the selected set of preconfigured values. A UE applying the same method is also provided.

Abstract: A battery device comprises a case, a core pack, a signal unit and a non-volatile memory, wherein the core pack, the signal unit and the non-volatile memory are disposed in the case. The case has a first transmission terminal and a second transmission terminal. The signal unit is electrically connected to the core pack and the first transmission terminal, and is configured to output a voltage signal associated with the state of the core pack through the first transmission terminal. The non-volatile memory is electrically connected to the second transmission terminal, and is configured to receive and store information associate with the core pack through the second transmission terminal.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.

Abstract: A method for a UE to monitor a PDCCH comprises receiving a first configuration from a base station to configure the UE with a first search space of the PDCCH, where the first search space is used for monitoring a scheduling signal used for indicating scheduling information, receiving a second configuration from the base station to configure the UE with a second search space of the PDCCH, wherein the second search space is used for monitoring a power saving signal used for indicating wake-up information associated with a DRX functionality, monitoring the first search space in response to the UE being in a DRX active time of the DRX functionality, wherein the DRX active time is a time during which the UE monitors the PDCCH, and not monitoring the second search space in response to the UE being in the DRX active time of the DRX functionality.

Abstract: A Class-D amplifier includes a loop filter circuit, a comparator circuitry, an output circuitry, and a common-mode control circuitry. The loop filter circuit generates first and second signals according to input and output signals and adjusts common-mode levels of the first and second signals according to a first common-mode signal. The comparator circuitry respectively compares a ramp signal with the first and second signals to generate pulse signals, and a common-mode level of the ramp signal is set based on a second common-mode signal. The output circuitry is powered by a power supply voltage to generate the output signals according to the pulse signals. The common-mode control circuitry performs an AC-coupling operation on the power supply voltage to generate a noise signal and generate one of the first and second common-mode signals according to the noise signal and another one of the first and second common-mode signals.

Abstract: Provided is an inductor structure and manufacturing method thereof, including forming an inductance coil in a semiconductor packaging carrier plate and disposing a patterned magnetic conductive layer in the inductance coil. Therefore, a patterned build-up wiring method is used to form a magnetic material in the carrier plate, thereby improving electrical characteristics of the inductor.

Abstract: Pesticidal compositions for improving physical characteristics of pesticide formulations which comprise natural pesticidal oil active ingredients are disclosed. One such composition comprises a pesticidal natural oil active ingredient, a surfactant to disperse the active ingredient in a water emulsion, a polymeric pour point depressant effective to reduce a pour point temperature of the pesticidal natural oil active ingredient and a hydrocarbon solvent. Methods for providing pesticidal compositions and application to control one or more pests are also disclosed.

Abstract: Provided is a core structure of an inductor element. The manufacturing method thereof is to embed a magnetic conductor including at least one magnetic conductive layer in a core body and to from a plurality of apertures for passing coils around the magnetic conductor in the core body. Accordingly, the magnetic conductor is designed in the core body by using the integrated circuit carrier board manufacturing process, such that the overall size and thickness of the inductor element can be greatly reduced, thereby facilitating product miniaturization using the inductor element.

Abstract: A pick-up structure of a memory device and a method of manufacturing the memory device are provided. The pick-up structure includes pick-up electrode stripes. Each pickup electrode stripe includes a main body portion in the peripheral pick-up region and an extending portion extending from the main body portion to the memory cell region. The extending portion is narrower than the main body portion. The sidewall surface of the extending portion is aligned with the sidewall surface of the main body portion.

Abstract: An annular optical element includes an outer annular surface, an inner annular surface, a first side surface, a second side surface and a plurality of strip-shaped wedge structures. The outer annular surface surrounds a central axis of the annular optical element and includes at least two shrunk portions. The first side surface connects the outer annular surface and the inner annular surface. The second side surface connects the outer annular surface and the inner annular surface, wherein the second side surface is disposed correspondingly to the first side surface. The strip-shaped wedge structures are disposed on the inner annular surface, wherein each of the strip-shaped wedge structures is disposed along a direction from the first side surface towards the second side surface and includes an acute end and a tapered portion connecting the inner annular surface and the acute end.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Abstract: An antenna module is provided, in which an antenna supporting substrate having a step-shaped hollow cavity is disposed on a circuit structure having an antenna part, so that the antenna part is exposed from the step-shaped hollow cavity, and an antenna structure is arranged on the steps of the step-shaped hollow cavity to cover the antenna part and is electromagnetically coupled with the antenna part, and there is no barrier but an air medium between the antenna structure and the antenna part.

Abstract: A camera driving module includes: a base including a central opening; a casing disposed on the base and including an opening hole corresponding to the central opening; a lens unit movably disposed on the casing; and a focus driving part. The focus driving part includes a carrier, an AF coil element, at least two permanent magnets and a Hall element. The carrier is disposed on the lens unit and movable in a direction parallel to an optical axis. The AF coil element is fixed to the base and faces toward the carrier. The permanent magnets are fixed on one side of the carrier facing toward the base and disposed opposite to each other about the optical axis. The Hall element faces toward a corresponding surface of one of the permanent magnets. The AF coil element and the corresponding surfaces are arranged in the direction parallel to the optical axis.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: A camera module includes a plastic carrier, an imaging lens assembly, a reflective element and a plurality of auto-focusing elements. The plastic carrier includes an inner portion and an outer portion, wherein an inner space is defined by the inner portion, and the outer portion includes at least one mounting structure. The imaging lens assembly is disposed in the inner space of the plastic carrier. The reflective element is for folding an image light by a reflective surface of the reflective element into the imaging lens assembly. The auto-focusing elements include at least two magnets and at least one wiring element, wherein the auto-focusing elements are for moving the plastic carrier along a second optical axis of the imaging lens assembly, and the magnets or the wiring element can be disposed on the mounting structure of the outer portion.

Abstract: A package structure is provided. The package structure includes an electronic component and a connection element. The electronic component includes a conductive wire and a magnetic layer encapsulating the conductive wire. The connection element penetrates and contacts the magnetic layer and the conductive wire.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.

Abstract: A lateral diffusion metal-oxide semiconductor (LDMOS) device includes a first gate structure and a second gate structure extending along a first direction on a substrate, a first source region extending along the first direction on one side of the first gate structure, a second source region extending along the first direction on one side of the second gate structure, a drain region extending along the first direction between the first gate structure and the second gate structure, a guard ring surrounding the first gate structure and the second gate structure, and a shallow trench isolation (STI) surrounding the guard ring.

Abstract: The present disclosure relates to systems and methods for real and virtual object interactions in augmented reality environments are disclosed. The system comprises areal object detection module to receive multiple image pixels and the corresponding depths of at least one initiative object, a real object recognition module to determine a shape, a position, and a movement of the initiative object; a virtual object display module to display a virtual target object, a collision module to determine whether the at least one initiative object collides into a virtual target object and, an interaction module for determining an action responding to an event based on at least one of an object recognition determination from the real object recognition module, a collision determination from the collision module, and a type of the virtual target object.