Abstract: An integrated, user-programmable interconnect architecture, includes a plurality of input/output pads arranged in a matrix of rows and columns, each of the input/output pads being connected to a first one of its row neighbors and a first one of its column neighbors by a two-state programmable interconnect element in series with a first three-state programmable interconnect element having first programming characteristics. A plurality of first conductors is generally disposed in a direction parallel to the rows, each of the rows having at least one of the first conductors connected through ones of the first three-state programmable interconnect elements to selected ones of the input/output pads associated therewith, at least one of the first conductors segmented by at least one of the two-state programmable interconnect elements.

Abstract: An interconnection element for use in an user-configurable interconnection technology includes a normally shorted fuse element and a normally open antifuse element connected in series. The antifuse element is designed to program at a first current at a selected programming voltage. The fuse element is designed to program at a second current which exceeds the first current by a margin sufficient to prevent inadvertent programming of fuse elements during the antifuse element programming cycle. An interconnection network for use in integrated circuits and other connection networks includes a plurality of circuit nodes which may be selectively connected to one another. Each circuit node is connected to other circuit nodes using the interconnection element of the present invention which includes an antifuse element which programs at a programming voltage and a first current in series with a fuse element which programs at a second current having a magnitude larger than the first current.

Abstract: In a programmed logic array (PLA) having a crosspoint AND plane and a crosspoint OR plane, each of these planes has input lines and output lines intersecting at crosspoints across each of which a transistor driver is connected or not, depending upon the details of the desired logic transformation function of the plane. Each output line is connected to a separate clocked pull-up (or precharge) transistor for precharging that line, and the source terminal of each driver is connected to a clocked pull-down transistor for logic evaluation or computation. In order to reduce the time needed for precharging, the source terminal of every driver is connected to another clocked pull-up transistor.

Abstract: A rapid and systematic method for performing chip layout of a random-logic IGFET circuit includes steps for arranging the device features and interconnection features corresponding to the circuit in respective positions in an array of intersecting rows and columns. The method provides layouts of device and interconnection features having a high packing density and a high degree of order and regularity to facilitate checking for layout errors.