Patents by Inventor Hung-Hsiang XSIAO

Hung-Hsiang XSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11657888
    Abstract: The disclosure provides a test platform and a redundancy fuse latch analysis method. In a DRAM chip, a first redundant memory cell group is used to repair a failed memory cell group. The DRAM chip performs a write operation for a repaired address corresponding to the failed memory cell group, so as to write identification data corresponding to the repaired address into a second redundant memory cell group actually corresponding to the repaired address. The DRAM chip performs a read operation for a redundancy address corresponding to the repaired address to read the readout data from the first redundant memory cell group corresponding to the redundancy address. The test platform compares the readout data with the identification data to verify whether the first redundant memory cell group corresponding to the redundancy address and the second redundant memory cell group actually corresponding to the repaired address are the same one.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: May 23, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hung-Hsiang Xsiao
  • Patent number: 10627442
    Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 21, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Shih-Ting Lin, Kung-Ming Fan, Hung-Hsiang Xsiao
  • Publication number: 20190178931
    Abstract: A method for estimating resistances of a source contact and a drain contact of a MOS transistor includes the following steps. A MOS transistor is provided. The MOS transistor includes a substrate, a gate, a source region and a drain region, a source contact electrically connected to the source region, and a drain contact electrically connected to the drain region. A resistance difference between a source contact resistance and a drain contact resistance is obtained. A resistance sum of the source contact resistance and the drain contact resistance is obtained. The source contact resistance and the drain contact resistance are calculated based on the resistance sum of the source contact resistance and the drain contact resistance, and on the resistance difference between the source contact resistance and the drain contact resistance.
    Type: Application
    Filed: March 5, 2018
    Publication date: June 13, 2019
    Inventors: Shih-Ting LIN, Kung-Ming FAN, Hung-Hsiang XSIAO