Patents by Inventor Hung-Jen Hsu

Hung-Jen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11989046
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Publication number: 20240138082
    Abstract: Methods, systems, and devices for providing computer implemented services are disclosed. To provide the computer implemented services, the quantity of hardware resources available for providing the computer implemented services may be modified. The quantity of hardware resources may be modified by adding removable cards to a host system. The host system may, while the added removable cards are cold, selectively warm the removable cards through conduction heating to retain their temperatures within operating temperature ranges.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: JULIAN YU-HAO CHEN, SHUN-CHENG HSU, HUNG-JEN CHEN
  • Publication number: 20240138101
    Abstract: Methods and systems for managing the operation of data processing systems are disclosed. A data processing system may include a computing device that may provide computer implemented services. To provide the computer implemented services, hardware components of the data processing system may need to operate in predetermined manners. To manage the operation of the hardware components, the data processing system may cool them when their temperatures fall outside of thermal operating ranges. To facilitate cooling, fans may be densely packed and arranged in a manner the occupies a majority of the space in a stack up. At least one side of the fans may be exposed and may not be covered.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: JULIAN YU-HAO CHEN, SHUN-CHENG HSU, HUNG-JEN CHEN
  • Patent number: 11929000
    Abstract: The display system comprising a main control module and a display module is provided. The main control module comprises a display driving circuit and a timing control circuit. The display driving circuit is used to output a display driving signal. The timing control circuit is coupled to the display driving circuit to receive the display driving signal, and convert the display driving signal into a digital signal. The display module comprises a first display panel to an N-th display panel, coupled to the timing control circuit and receiving the digital signal, so as to display corresponding multimedia content according to the digital signal, wherein N is a positive integer greater than 1, and the main control module is independently coupled to the display module.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: March 12, 2024
    Assignee: AUO Display Plus Corporation
    Inventors: Sheng-Kai Hsu, Hung-Min Shih, Yung-Jen Chen
  • Patent number: 11916043
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Min Lin, Hung-Jen Hsu, Dun-Nian Yaung
  • Publication number: 20230397509
    Abstract: In an embodiment, a method includes: growing a phase change material on a platform configured for a semiconductor workpiece process; setting the phase change material to an amorphous state; performing the semiconductor workpiece process within a semiconductor processing chamber; and measuring resistance across two points along the phase change material.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 7, 2023
    Inventors: Chien-Mao CHEN, Hung-Jen HSU
  • Patent number: 11812674
    Abstract: In an embodiment, a method includes: growing a phase change material on a platform configured for a semiconductor workpiece process; setting the phase change material to an amorphous state; performing the semiconductor workpiece process within a semiconductor processing chamber; and measuring resistance across two points along the phase change material.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Mao Chen, Hung-Jen Hsu
  • Publication number: 20230139843
    Abstract: A semiconductor device includes a first semiconductor die. The semiconductor device includes a redistribution structure disposed over a first side of the first semiconductor die and comprising a plurality of layers. At least a first one of the plurality of layers comprises a first power/ground plane embedded in a dielectric material and configured to provide a first supply voltage for the first semiconductor die. The first power/ground plane encloses a plurality of first conductive structures that are each operatively coupled to the first semiconductor die, and a plurality of second conductive structures scattered around the plurality of first conductive structures.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 4, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jen Hsu, Fong-yuan Chang, Shuo-Mao Chen
  • Publication number: 20220392873
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes forming a first wafer including a plurality of electronic integrated circuits (EICs), forming a second wafer including a plurality of photonic integrated circuits (PICs), bonding the first wafer to the second wafer to form a first stacked wafer. The bonding of the first wafer to the second wafer includes vertically aligning each of the plurality of the EICs with one of the plurality of the PICs.
    Type: Application
    Filed: July 28, 2021
    Publication date: December 8, 2022
    Inventors: Chin-Min Lin, Hung-Jen Hsu, Dun-Nian Yaung
  • Publication number: 20220139988
    Abstract: A semiconductor device structure for sensing an incident light includes a substrate, a passivation layer and a wiring structure. The substrate has a device embedded therein. The passivation layer is disposed on the substrate, where the passivation layer has a first side and a second side opposite to the first side, the first side of the passivation layer includes microstructures disposed on the substrate, and the second side of the passivation layer is a continuous flat plane, wherein each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed on the substrate, where the writing structure includes at least one contact and metal interconnection patterns respectively formed in different dielectric layers, and the at least one contact and the metal interconnection patterns are electrically connected, where the substrate is located between the passivation layer and the wiring structure.
    Type: Application
    Filed: January 17, 2022
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ping Pan, Hung-Jen Hsu
  • Patent number: 11227887
    Abstract: A semiconductor device structure for sensing an incident light includes a substrate, a passivation layer and a wiring structure. The substrate has a device embedded therein. The passivation layer is disposed on the substrate, where the passivation layer has a first side and a second side opposite to the first side, the first side of the passivation layer includes microstructures disposed on the substrate, and the second side of the passivation layer is a continuous flat plane, wherein each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed on the substrate, where the writing structure includes at least one contact and metal interconnection patterns respectively formed in different dielectric layers, and the at least one contact and the metal interconnection patterns are electrically connected, where the substrate is located between the passivation layer and the wiring structure.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ping Pan, Hung-Jen Hsu
  • Publication number: 20210288254
    Abstract: In an embodiment, a method includes: growing a phase change material on a platform configured for a semiconductor workpiece process; setting the phase change material to an amorphous state; performing the semiconductor workpiece process within a semiconductor processing chamber; and measuring resistance across two points along the phase change material.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Inventors: Chien-Mao Chen, Hung-Jen Hsu
  • Patent number: 11031556
    Abstract: In an embodiment, a method includes: growing a phase change material on a platform configured for a semiconductor workpiece process; setting the phase change material to an amorphous state; performing the semiconductor workpiece process within a semiconductor processing chamber; and measuring resistance across two points along the phase change material.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Mao Chen, Hung-Jen Hsu
  • Publication number: 20200185603
    Abstract: In an embodiment, a method includes: growing a phase change material on a platform configured for a semiconductor workpiece process; setting the phase change material to an amorphous state; performing the semiconductor workpiece process within a semiconductor processing chamber; and measuring resistance across two points along the phase change material.
    Type: Application
    Filed: April 2, 2019
    Publication date: June 11, 2020
    Inventors: Chien-Mao CHEN, Hung-Jen HSU
  • Publication number: 20200052025
    Abstract: A semiconductor device structure for sensing an incident light includes a substrate, a passivation layer and a wiring structure. The substrate has a device embedded therein. The passivation layer is disposed on the substrate, where the passivation layer has a first side and a second side opposite to the first side, the first side of the passivation layer includes microstructures disposed on the substrate, and the second side of the passivation layer is a continuous flat plane, wherein each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed on the substrate, where the writing structure includes at least one contact and metal interconnection patterns respectively formed in different dielectric layers, and the at least one contact and the metal interconnection patterns are electrically connected, where the substrate is located between the passivation layer and the wiring structure.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ping Pan, Hung-Jen Hsu
  • Patent number: 10475835
    Abstract: A semiconductor device structure for sensing an incident light includes a substrate, a wiring structure, and at least one passivation layer. The substrate has a device. The at least one passivation layer is disposed above the wiring structure. The at least one passivation layer includes a plurality of microstructures, and each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed below the at least one passivation layer. A method for manufacturing the semiconductor device structure is also provided.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ping Pan, Hung-Jen Hsu
  • Publication number: 20180069043
    Abstract: A semiconductor device structure for sensing an incident light includes a substrate, a wiring structure, and at least one passivation layer. The substrate has a device. The at least one passivation layer is disposed above the wiring structure. The at least one passivation layer includes a plurality of microstructures, and each of the microstructures has a cross-section in a shape of a triangle, trapezoid or arc. The wiring structure is disposed below the at least one passivation layer. A method for manufacturing the semiconductor device structure is also provided.
    Type: Application
    Filed: September 5, 2016
    Publication date: March 8, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ping Pan, Hung-Jen Hsu
  • Patent number: 9865929
    Abstract: A communication device includes a ground element and an antenna element. The antenna element is disposed adjacent to an edge of the ground element. The antenna element includes a first metal element and a second metal element. The first metal element has a first end and a second end. The first end is coupled through a capacitive element to a communication module. The second end is coupled through a shorting element to the ground element. The second metal element has a third end and a fourth end. The third end is coupled to the communication module. The fourth end is open. The first metal element and the second metal element are adjacent to each other, but not connected to each other. The first metal element and the second metal element have projections on the edge of the ground element, wherein the projections do not overlap with each other.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: January 9, 2018
    Assignee: ACER INCORPORATED
    Inventors: Kin-Lu Wong, Hung-Jen Hsu
  • Patent number: 9437925
    Abstract: A communication device including a ground element and an antenna element is provided. The antenna element is disposed adjacent to an edge of the ground element. The antenna element includes a loop metal element and a branch metal element. The loop metal element has a first end and a second end. The first end is coupled to a signal source. The second end is coupled to the ground element. The loop metal element includes a first segment and a second segment. The first segment is separated from the second segment by a gap. The first segment includes the first end, and the second segment includes the second end. The branch metal element has a third end and a fourth end. The third end is coupled through an inductive element to a connection point on the loop metal element. The fourth end is open.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 6, 2016
    Assignee: ACER INCORPORATED
    Inventors: Kin-Lu Wong, Hung-Jen Hsu
  • Patent number: 9385419
    Abstract: A communication device, including a device casing, an external connection element, and a first metal element, is provided. A ground element and an antenna element are disposed in the device casing. The ground element has a first edge, a second edge, and a first connection point. The first edge and the second edge are opposite to each other. The first connection point is disposed near or at the second edge. The antenna element is disposed near the first edge. The external connection element is formed by a non-conductive material and is outside the device casing. The external connection element has a belt-like structure and is combined with the device casing to substantially form a loop structure. The first metal element is supported by the external connection element and is coupled to the first connection point of the ground element.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: July 5, 2016
    Assignee: Acer Incorporated
    Inventors: Kin-Lu Wong, Hung-Jen Hsu