Patents by Inventor Hung-Jen Lin

Hung-Jen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130075139
    Abstract: A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI includes a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A solder ball is over the PPI. A compound includes a portion adjoining the solder ball and the polymer layer, wherein the compound includes flux and a polymer.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Ding Wang, Hung-Jen Lin, Chien-Hsiun Lee
  • Patent number: 7679972
    Abstract: Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: March 16, 2010
    Assignee: Spansion LLC
    Inventors: Jinsook Kim, Nian Yang, Hung-Jen Lin, Sachit Chandra
  • Publication number: 20090129172
    Abstract: Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Applicant: SPANSION LLC
    Inventors: Jinsook Kim, Nian Yang, Hung-Jen Lin, Sachit Chandra
  • Patent number: 7176081
    Abstract: A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Fu Chang, Yen-Hsiu Chen, Hung-Jen Lin, Ming-Chu King, Ching-Hwanq Su, Chih-Mu Huang, Yun Chang
  • Publication number: 20050260811
    Abstract: A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.
    Type: Application
    Filed: May 20, 2004
    Publication date: November 24, 2005
    Inventors: Chih-Fu Chang, Yen-Hsiu Chen, Hung-Jen Lin, Ming-Chu King, Ching-Hwano Su, Chih-Mu Huang, Yun Chang
  • Patent number: 6949471
    Abstract: A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: September 27, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chen Hao, Hung-Jen Lin, Min-Hwa Chi, Chih-Heng Shen
  • Publication number: 20050026406
    Abstract: A method of fabricating polysilicon patterns. The method includes depositing polysilicon on a substrate. The polysilicon may be doped or pre-doped depending upon the application. A mask layer is applied and patterned. Thereafter, the polysilicon is etched to form the polysilicon patterns and an oxidizing step is performed. The mask layer is removed after the oxidizing step is performed.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 3, 2005
    Inventors: Ching-Chen Hao, Hung-Jen Lin, Min-Hwa Chi, Chih-Heng Shen
  • Patent number: 6777708
    Abstract: Methods and systems are described for determining floating body delay effects in an SOI wafer, wherein test apparatus is provided in a wafer comprising a plurality of floating body devices fabricated in series in the wafer, and a pulse generation circuit providing a pulse output corresponding to a delay time associated with the floating body chain according to an input pulse edge and a propagated pulse edge from the floating body devices.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: August 17, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hung-Jen Lin, W. Eugene Hill
  • Patent number: 6774395
    Abstract: Methods are described for characterizing floating body delay effects in SOI wafers comprising providing a pulse edge to a floating body and a tied body chain in the wafer, storing tied body chain data according to one or more of the floating body devices, and characterizing the floating body delay effects according to the stored tied body chain data. Test apparatus are also described comprising a floating body chain including a plurality of series connected floating body inverters or NAND gates fabricated in the wafer and a tied body chain comprising a plurality of series connected tied body devices to in the wafer. Storage devices are coupled with the tied body devices and with one or more of the floating body devices and operate to store tied body chain data from the tied body devices according to one or more signals from floating body chain.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: August 10, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hung-Jen Lin, W Eugene Hill, Mario M. Pelella, Chern-Jann Lee, Srikanth Sundararajan, Siu May Ho
  • Patent number: 6638409
    Abstract: A real-time and in-line process control system maintains stable plating performance in copper electrochemical plating IC devices by using a real time, on-line programmable controller. Two or more valves to direct the flow of the electrolyte from the electroplating cell back to the reservoir connect an alternative carbon-filter as well as a mirco-filter. The programmable controller controls the operation of at least two in-line valves to direct the flow of the electrolyte within the system.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: October 28, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Ming Huang, Li-Chuen Cheng, Hung-Jen Lin, Chih-Chen Ku, San-Sun Yang