Abstract: The present invention provides a remote control system for a power supply, comprising a display data channel (DDC); a first control circuit electrically connected to said DDC, coding and sending a control signal through said DDC to control said power supply; a second control circuit electrically connected to said DDC, receiving and decoding said control signal through said DDC to control said power supply.

Abstract: An apparatus and method for data capture with multi-threshold decision technique is disclosed. An apparatus for data capture with multi-threshold decision technique comprises a capture engine unit being operative to captures data from a video source, a buffer unit being operative to store the captured data by the capture engine unit, and a comparison unit being operative to compare the captured data stored in the buffer unit with a newly captured data outputted from the capture engine unit, wherein the comparison unit utilizes different thresholds to distinguish the difference degree between the captured data stored in the buffer unit and a newly captured data outputted from the capture engine unit so as to determine whether performing data update or not.

Abstract: A method and apparatus for improving bandwidth for depth information communication in a computer graphics system. In operation, a decoder checks a type table associated with a collection of pixels in a memory unit in response to a request for depth information with respect to the collection of pixels. If the type table indicates that the depth information with respect to the collection of pixels has been encoded previously, the decoder computes depth values corresponding to the collection of pixels for each visible polygon in accordance with respective sets of plane parameters in a parameter record associated with a plane pattern, and reconstructs the depth information from the depth values for each visible polygon in accordance with the plane pattern. When the collection of pixels is modified by a new polygon, an encoder updates the plane pattern, the parameter record, and the type table in the memory unit.

Abstract: A computer network architecture for providing display data at a remote monitor is disclosed. The computer network architecture comprises a local computer, a local user interface controller, a remote user interface controller, and a remote monitor. The local user interface controller electrically connected to the local computer comprises a video compressor, a display timing capture controller, a DDC interface, and a network controller. The remote user interface controller be capable of communicating with the local user interface controller through a network comprises a network controller, a video decompressor, a display timing generator, and a DDC interface. The monitor electrically to the remote user interface controller is used for receiving the decompressed video signals, output signals generated by the display timing generator, and the data structure and displaying the decompressed video signals on the monitor.

Abstract: A progressive differential motion JPEG codec is disclosed. The compression encoder of the progressive differential motion JPEG codec comprises a video capture unit, a video capture buffer, a detection unit, a compression unit, and a quality level buffer. The video capture unit is used for receiving an image data and dividing a component of the image data into a plurality of image data blocks. The video capture buffer stores the image data block. The detection unit is electrically coupled to the video capture unit and the video capture buffer for detecting whether a content of the image data block input from the video capture unit is different from a content of the image data block retrieved from the video capture buffer.

Abstract: A method and apparatus for improving bandwidth for depth information communication in a computer graphics system. In operation, a decoder checks a type table associated with a collection of pixels in a memory unit in response to a request for depth information with respect to the collection of pixels. If the type table indicates that the depth information with respect to the collection of pixels has been encoded previously, the decoder computes depth values corresponding to the collection of pixels for each visible polygon in accordance with respective sets of plane parameters in a parameter record associated with a plane pattern, and reconstructs the depth information from the depth values for each visible polygon in accordance with the plane pattern. When the collection of pixels is modified by a new polygon, an encoder updates the plane pattern, the parameter record, and the type table in the memory unit.

Abstract: A color processing method enhances color intensity and saturation in RGB domain. For a pixel to be enhanced, a new set of color values, (R′,G′,B′), are computed base on its original color values, (R,G,B). The original red, green, and blue intensity values are used to obtain a scaling factor and an intensity base. The scaling factor is then compared with a user controlled scaling factor to obtain a final scaling factor. The new set of color values are computed based on the final scaling factor and the intensity base to enhance the intensity and saturation of the pixel.

Abstract: An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Abstract: A method and a computer system are provided for using a portion of a local memory of a graphics card as an extensive memory of a system memory. When the computer system is rebooted, a portion of a local memory of a graphics card is claimed as an extensive memory of the system memory, and the local memory excluding the extensive memory is claimed a new local memory by a driver of the graphics card. The driver of the graphics card reports the new local memory capacity to an operating system of the computer. Then, a new system memory capacity including the extensive memory and the original system memory is claimed by a chipset of the computer system and reported to a memory sizing command of BIOS. Finally, if a memory access request is within the address range of the extensive memory, the memory access request is transmitted to the graphics card through AGP/PCI bus.

Abstract: An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Abstract: The present invention provides a circuit for adjusting operating frequency of a chip, and comprises an oscillator, a controlling circuit, and a voltage adjusting circuit. The oscillator is coupled to the chip for outputting a testing clock signal according to a voltage signal. The controlling circuit is coupled to the oscillator for comparing the testing clock signal and a predetermined clock frequency, then outputting a voltage controlling signal. The voltage adjusting circuit is coupled to the controlling circuit for adjusting the voltage value of the voltage signal according to the voltage controlling signal.

Abstract: A digital clock throttling device, for gating a clock signal of a circuit, at least includes an accumulator and a gating circuit. The accumulator responsive to a throttling value generates a first output signal. The first output signal is divided into a throttling signal with a most significant bit and a feedback signal with rest bits of the first output signal except for the most significant bit. The feedback signal is sent to the accumulator back for accumulating to the throttling value as the first output signal. The gating circuit coupling with the accumulator responsive to the throttling signal and clock signal gates out some clock cycles of the clock signal, thereby providing a gated clock signal in an adjusted frequency.

Abstract: A method for contrast enhancement of pixel data of a decompressed color image includes the steps of computing I component values in an HSI color space for the pixel data of the color image, computing an image I component value which is an average of the computed I component values, and enhancing each of the pixel data of the color image according to the image I component value. An apparatus for contrast enhancement of pixel data of a decompressed color image is also disclosed.

Abstract: A method and system for compressing graphic data by dividing the data into segments is disclosed. The size of the divided segment is programmable. A frame buffer partitioned into a compressed frame buffer and an uncompressed frame buffer stores graphic data. Each segment of the graphic data is compressed by three different algorithms that encode the graphic data as a plurality of code-words. Each code-word for the segment is taken from the algorithm that can compress the largest number of pixels in the code-word. A header is used to indicate the number of code-words and the compression method used in each code-word. The total number of bytes obtained from the compression of a segment is compared to a pre-defined limit to determine if the compression of the segment is successful. The successfully compressed data of a segment are written to the compressed frame buffer. A compression status flag buffer is used to identify if a segment is compressed or not.

Abstract: A shared memory architecture of graphics frame buffer and hard disk cache is presented. The architecture includes a system bus interface, a hard disk controller, a graphics controller, an arbiter, a memory and a shared memory block. The shared memory block is divided into graphics frame buffer memory and hard disk controller cache memory. The arbiter determines the shared memory access priority between the graphics controller and the hard disk controller. By mean of hardware implementation, memories can be shared by the graphics controller and the disk controller. The complexity of the system is reduced and the system performance is enhanced. The overall system cost is decreased.