Patents by Inventor Hung-Jung Tu
Hung-Jung Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9406650Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.Type: GrantFiled: April 21, 2014Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Wen-Chih Chiou, Tu-Hao Yu, Hung-Jung Tu, Yu-Liang Lin, Shih-Hui Wang
-
Patent number: 9390949Abstract: This description relates to a wafer debonding and cleaning apparatus including an automatic wafer handling module. The automatic wafer handling module loads a semiconductor wafer into a wafer debonding module for a debonding process. The automatic wafer handling module removes the semiconductor wafer from the debonding module and loads the semiconductor wafer into a wafer cleaning module for a cleaning process.Type: GrantFiled: November 29, 2011Date of Patent: July 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chih Chiou, Yu-Liang Lin, Hung-Jung Tu
-
Patent number: 9305769Abstract: A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.Type: GrantFiled: January 16, 2014Date of Patent: April 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Shin-Puu Jeng, Hung-Jung Tu
-
Publication number: 20160035609Abstract: A wafer cassette includes a main body having space to hold at least one wafer assembly. Each of the at least one wafer assembly includes a wafer and an electrostatic carrier attached to the wafer. An electrical contact structure inside the main body is arranged to contact an electrical pad of the electrostatic carrier.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Inventors: Wen-Chih Chiou, Yung-Chi Lin, Yu-Liang Lin, Hung-Jung Tu
-
Publication number: 20150221611Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.Type: ApplicationFiled: April 21, 2014Publication date: August 6, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Puu Jeng, Wen-Chih Chiou, Tu-Hao Yu, Hung-Jung Tu, Yu-Liang Lin, Shih-Hui Wang
-
Patent number: 9093489Abstract: Embodiments of the present disclosure include methods of forming a semiconductor device. An embodiment is a method for forming a semiconductor device, the method including applying a substrate to a carrier with an adhesive layer between the carrier and the substrate, curing a portion of the adhesive layer, the cured portion surrounding an uncured portion of the adhesive layer, removing the carrier from adhesive layer, removing the uncured portion of the adhesive layer, and removing the cured portion of the adhesive layer.Type: GrantFiled: May 17, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tu-Hao Yu, Wen-Chih Chiou, Hung-Jung Tu, Yu-Liang Lin
-
Publication number: 20140374031Abstract: A wafer debonding and cleaning apparatus comprises a wafer debonding module configured to separate a semiconductor wafer from a carrier wafer. The wafer debonding and cleaning apparatus also comprises a first wafer cleaning module configured perform a first cleaning process to clean a surface of the semiconductor wafer. The wafer debonding and cleaning apparatus further comprises an automatic wafer handling module configured to transfer the semiconductor wafer from one of the wafer debonding module or the first wafer cleaning module to the other of the wafer debonding module or the first wafer cleaning module. The semiconductor wafer has a thickness ranging from about 0.20 ?m to about 3 mm.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: Wen-Chih CHIOU, Yu-Liang LIN, Hung-Jung TU
-
Publication number: 20140261997Abstract: Embodiments of the present disclosure include methods of forming a semiconductor device. An embodiment is a method for forming a semiconductor device, the method including applying a substrate to a carrier with an adhesive layer between the carrier and the substrate, curing a portion of the adhesive layer, the cured portion surrounding an uncured portion of the adhesive layer, removing the carrier from adhesive layer, removing the uncured portion of the adhesive layer, and removing the cured portion of the adhesive layer.Type: ApplicationFiled: May 17, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tu-Hao Yu, Wen-Chih Chiou, Hung-Jung Tu, Yu-Liang Lin
-
Patent number: 8759150Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.Type: GrantFiled: June 4, 2012Date of Patent: June 24, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Pin Hu, Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou, Hung-Jung Tu
-
Patent number: 8749027Abstract: A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure.Type: GrantFiled: January 7, 2009Date of Patent: June 10, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Shin-Puu Jeng, Hung-Jung Tu, Wen-Chih Chiou
-
Publication number: 20140130962Abstract: A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua YU, Kuo-Ching HSU, Chen-Shien CHEN, Ching-Wen HSIAO, Wen-Chih CHIOU, Shin-Puu JENG, Hung-Jung TU
-
Patent number: 8664749Abstract: A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film.Type: GrantFiled: April 11, 2011Date of Patent: March 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang, Jung-Chih Hu, Wen-Chih Chiou
-
Patent number: 8629066Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.Type: GrantFiled: July 30, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
-
Publication number: 20130133688Abstract: This description relates to a wafer debonding and cleaning apparatus including an automatic wafer handling module. The automatic wafer handling module loads a semiconductor wafer into a wafer debonding module for a debonding process. The automatic wafer handling module removes the semiconductor wafer from the debonding module and loads the semiconductor wafer into a wafer cleaning module for a cleaning process.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chih CHIOU, Yu-Liang LIN, Hung-Jung TU
-
Patent number: 8405225Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.Type: GrantFiled: April 2, 2012Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang
-
Patent number: 8319349Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.Type: GrantFiled: January 3, 2012Date of Patent: November 27, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Pin Hu, Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou, Hung-Jung Tu
-
Publication number: 20120289062Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.Type: ApplicationFiled: July 30, 2012Publication date: November 15, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
-
Publication number: 20120238057Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.Type: ApplicationFiled: June 4, 2012Publication date: September 20, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsien-Pin Hu, Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Jing-Cheng Lin, Wen-Chih Chiou, Hung-Jung Tu
-
Patent number: 8264066Abstract: An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.Type: GrantFiled: November 13, 2009Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Lo, Hung-Jung Tu, Hai-Ching Chen, Tien-I Bao, Wen-Chih Chiou, Chen-Hua Yu
-
Publication number: 20120187576Abstract: A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die.Type: ApplicationFiled: April 2, 2012Publication date: July 26, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Wen-Chih Chiou, Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang