Patents by Inventor Hung-Li Chang
Hung-Li Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991485Abstract: A projection apparatus including a projection device, a reflecting component, and an image capturing device is provided. The projection device is adapted to project an image light beam to form a projection image. The reflecting component is disposed on the projection device and has a reflecting surface. The image capturing device is disposed on the projection device and has an image capturing end. The image capturing end faces the reflecting surface. The reflecting surface is adapted to reflect the projection image to the image capturing end.Type: GrantFiled: July 12, 2022Date of Patent: May 21, 2024Assignee: Coretronic CorporationInventors: Jen-Yu Shie, Kuang-Hsiang Chang, Hung-Pin Chen, Heng Li
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Publication number: 20240145653Abstract: A manufacturing method of a display device includes forming light emitting components on a first substrate, the light emitting components include a first side and a second side, and the second side is away from the first substrate; forming a circuit layer on the first substrate and on the second side of the light emitting components; forming a first protective layer on the circuit layer and forming an insulating layer on the first protective layer; removing the first substrate after forming a second substrate on the insulating layer; forming a black matrix layer on the first side of the light emitting components, and the black matrix layer includes openings; forming light conversion layers in the openings of the black matrix layer; forming a second protective layer on the black matrix layer and the light conversion layers; and forming a third substrate on the second protective layer.Type: ApplicationFiled: May 12, 2023Publication date: May 2, 2024Applicant: HANNSTAR DISPLAY CORPORATIONInventors: Chun-I Chu, Yu-Chi Chiao, Yung-Li Huang, Hung-Ming Chang, Cheng-Yu Lin, Huan-Hsun Hsieh, CHeng-Pei Huang
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Publication number: 20240088267Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
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Patent number: 11929115Abstract: A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.Type: GrantFiled: April 8, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jer-Fu Wang, Hung-Li Chiang, Yi-Tse Hung, Tzu-Chiang Chen, Meng-Fan Chang
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Patent number: 10892208Abstract: An improved heat dissipation apparatus for limiting the temperature of multiple power semiconductors featuring flow balancers to manipulate the hydrodynamic pressure of the coolant fluid to regulate the coolant fluid flow distribution across the heat exchange fins to either create uniform flow distribution or purposefully disproportionate or custom coolant fluid flow distribution for the purpose of achieving higher heat transfer efficiency.Type: GrantFiled: October 19, 2017Date of Patent: January 12, 2021Assignee: BEIJING E. MOTOR ADVANCE CO. LTD.Inventors: Hung-Li Chang, Lon C. Cooper, David L. Bogdanchik
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Publication number: 20200375069Abstract: An improved power semiconductor heat dissipation apparatus for regulating the temperature of multiple power semiconductors featuring increased structural integrity for high pressure applications, a more robust heat exchange fin design to accommodate particulates or other solid contaminants that may be present in less refined coolant fluids, and a modified construction for increased durability and ease of automated assembly.Type: ApplicationFiled: April 22, 2019Publication date: November 26, 2020Inventors: Yoatian Zhang, George R. Woody, Hung-Li Chang, Paul F. Carosa, Ramiro R. Montalvo
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Publication number: 20190139862Abstract: An improved heat dissipation apparatus for limiting the temperature of multiple power semiconductors featuring flow balancers to manipulate the hydrodynamic pressure of the coolant fluid to regulate the coolant fluid flow distribution across the heat exchange fins to either create uniform flow distribution or purposefully disproportionate or custom coolant fluid flow distribution for the purpose of achieving higher heat transfer efficiency.Type: ApplicationFiled: October 19, 2017Publication date: May 9, 2019Inventors: HUNG-LI CHANG, Lon C. Cooper, David L. Bogdanchik
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Patent number: 9219012Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: GrantFiled: November 11, 2011Date of Patent: December 22, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
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Publication number: 20120056295Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: ApplicationFiled: November 11, 2011Publication date: March 8, 2012Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: CHIH-PING LIN, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
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Patent number: 8080455Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: GrantFiled: July 22, 2008Date of Patent: December 20, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
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Patent number: 8063439Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: GrantFiled: November 23, 2010Date of Patent: November 22, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
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Publication number: 20110062500Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: ApplicationFiled: November 23, 2010Publication date: March 17, 2011Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
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Patent number: 7863147Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: GrantFiled: July 22, 2008Date of Patent: January 4, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
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Publication number: 20090236681Abstract: A method for fabricating a semiconductor device is provided. A substrate comprising a P-well is provided. A low voltage device area and a high voltage device area are defined in the P-well. A photoresist layer is formed on the substrate. A photomask comprising a shielding region is provided. The shielding region is corresponded to the high voltage device area. A pattern of the photomask is transferred to the photoresist layer on the substrate by a photolithography process using the photomask. A P-type ion field is formed outside of the high-voltage device area by selectively doping P-type ions into the substrate using the photoresist layer as a mask.Type: ApplicationFiled: July 22, 2008Publication date: September 24, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang
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Publication number: 20090236665Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.Type: ApplicationFiled: July 22, 2008Publication date: September 24, 2009Applicant: VANGUARD INTERNATIONAL SEMICONDUCTORInventors: Chih-Ping Lin, Pi-Kuang Chuang, Hung-Li Chang, Shih-Ming Chen, Hsiao-Ying Yang, Ya-Sheng Liu
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Publication number: 20080067638Abstract: A chip-scale packaging leadframe for a memory chip is provided, where the external leads of at least a pair of the VDD leads and at least a pair of the VSS leads are arranged on two parallel and opposing sides, namely, the first side and the third side, respectively, while all or almost all external leads of the other leads are arranged on the other two parallel and opposing sides, namely, the second side and the fourth side, respectively. According to the present invention, the dimension of the external leads of the VDD and VSS leads should be at least 0.4×1.15 mm; or the area of the external leads of the VDD and VSS leads should be at least 1.8 times of that of the other leads. Also according to the present invention, the gap of the external leads of adjacent VDD and VSS leads should be at least 1.0 mm; or at least two times of that of the other leads.Type: ApplicationFiled: September 18, 2006Publication date: March 20, 2008Inventors: Hung-Li Chang, Jack C. Huang, Clement Ho