Patents by Inventor Hung-Lin Chen

Hung-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200164482
    Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.
    Type: Application
    Filed: September 3, 2019
    Publication date: May 28, 2020
    Inventors: Shih-Chung Chen, Yi-Shao Lin, Sheng-Tai Peng, Ya-Jen Sheuh, Hung-Lin Chen, Ren-Dou Lee
  • Publication number: 20200115456
    Abstract: Provided herein is a novel antibody exhibiting binding affinity and specificity to galectin-7. Also provided herein are methods for treating psoriasis or cancer in a subject by administering to the subject a drug selected with the aid of the present anti-galectin-7 antibody.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 16, 2020
    Applicant: Academia Sinica
    Inventors: Fu-Tong LIU, Hung-Lin CHEN, Po-Cheng CHIANG
  • Publication number: 20200081332
    Abstract: An illumination system, a projection apparatus and an illumination control method are provided. The illumination system includes an excitation light source, an optical component, a light source driver, a temperature sensing module and a controller. The excitation light source emits an excitation light beam. The optical component is located on a transmission path of the excitation light beam. The light source driver is configured to drive the excitation light source. The temperature sensing module is located in a neighboring region of the optical component and configured to sense a temperature of the neighboring region of the optical component to output a sensing voltage. The controller is configured to receive the sensing voltage to determine whether the sensing voltage falls out of a predetermined voltage range and configured to output a control signal to the light source driver to adjust the excitation light beam.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 12, 2020
    Applicant: Coretronic Corporation
    Inventors: Chen-Cheng Chou, Jeng-An Liao, Chun-Hsien Wu, Fu-Shun Kao, Hung-Lin Chen, Hsin-Chang Huang
  • Patent number: 10586705
    Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Lin Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Po-Ming Chen, Tza-Hao Wang
  • Publication number: 20200073221
    Abstract: A projection device, a light source system and a projection method thereof are provided. A portion of the light-emitting units are controlled to provide a light beam as the first light beam. It is detected whether characteristic parameters of the light-emitting units providing the light beam reach a preset value. When the preset value is not reached, the light-emitting units providing the light beam are disabled, and the remaining light-emitting units are controlled to provide the back-up light beam as the first light beam. A portion of the first light beam is converted into a second light beam. The first light beam of which the wavelength is not converted and the second light beam are combined to generate an illumination beam. The illumination beam is converted into an image beam. The image beam is converted into a projection beam.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 5, 2020
    Applicant: Coretronic Corporation
    Inventors: Chen-Cheng Chou, Jeng-An Liao, Fu-Shun Kao, Hung-Lin Chen, Hsin-Chang Huang
  • Publication number: 20190165180
    Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.
    Type: Application
    Filed: February 23, 2018
    Publication date: May 30, 2019
    Inventors: Hung-Lin CHEN, Shiuan-Jeng Lin, Wen-Chih Chiang, Po-Ming Chen, Tza-Hao Wang
  • Patent number: 9966427
    Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Hung-Lin Chen, Jui-Chun Weng, Shiuan-Jeng Lin, Tian Sheng Lin, Yu-Jui Wu, Albion Pan, Bob Sun
  • Patent number: 9865609
    Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Lin Chen, Shyh-Wei Cheng, Che-Jung Chu
  • Publication number: 20170330931
    Abstract: A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 16, 2017
    Inventors: Shyh-Wei Cheng, Hung-Lin Chen, Jui-Chun Weng, Shiuan-Jeng Lin, Tian Sheng Lin, Yu-Jui Wu, Albion Pan, Bob Sun
  • Publication number: 20170221910
    Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Hung-Lin Chen, Shyh-Wei Cheng, Che-Jung Chu
  • Publication number: 20150033142
    Abstract: A method for managing IM services and an electronic device using the same are provided. The method includes determining whether identification information respectively recorded in a first electronic device and a second electronic device is consistent when the first electronic device and the second electronic device are connected to each other through a network. The method also includes transmitting, by the second electronic device, at least one IM login information stored therein to the first electronic device if the identification information respectively recorded in the first electronic device and the second electronic device is consistent. The method further includes when a function button corresponding to a login function of the first electronic device receives a selection operation, executing, by the first electronic device, an IM service login procedure by using the at least one IM login information received from the second electronic device.
    Type: Application
    Filed: November 29, 2013
    Publication date: January 29, 2015
    Applicant: Wistron Corporation
    Inventors: Yung-Yen Chang, Hung-Lin Chen
  • Patent number: 8669641
    Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chang Hsieh, Hung-Lin Chen, Hsiu-Mei Yu, Chin Kun Lan, Dong-Lung Lee
  • Patent number: 8107817
    Abstract: A method for receiving an optical orthogonal frequency-division multiplexing (OFDM) signal and a receiver thereof are applicable to an optical OFDM system. The receiving method includes the following steps. An optical signal is converted into a digital signal. A symbol boundary of the digital signal is estimated. A guard interval of the digital signal is removed according to the symbol boundary, so as to generate an electrical signal. The electrical signal is converted into a plurality of frequency domain sub-carriers in a fast Fourier transform (FFT) manner. A timing offset is estimated with pilot carriers and frequency domain sub-carriers corresponding to the same symbol period. The estimated symbol boundary is compensated with the timing offset. Each frequency domain sub-carrier includes a plurality of pilot carrier signals. Through the receiving method, the timing offset arisen from chromatic dispersion of an optical fiber is effectively estimated and adopted for compensation.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 31, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Dar-Zu Hsu, Hung-Lin Chen
  • Publication number: 20110241179
    Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chang Hsieh, Hung-Lin Chen, Hsiu-Mei Yu, Chin Kun Lan, Dong-Lung Lee
  • Patent number: 7968431
    Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: June 28, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chang Hsieh, Hung-Lin Chen, Hsiu-Mei Yu, Chin Kun Lan, Dong-Lung Lee
  • Publication number: 20110084391
    Abstract: An integrated circuit structure includes a semiconductor substrate; a first titanium layer over the semiconductor substrate, wherein the first titanium layer has a first thickness less than 130 ?; a first titanium nitride layer over and contacting the first titanium layer; and an aluminum-containing layer over and contacting the first titanium nitride layer.
    Type: Application
    Filed: July 23, 2010
    Publication date: April 14, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shyh-Wei Cheng, Pin-Shyne Chin, Kuo-Chio Liu, Che-Jung Chu, Ming-Chang Hsieh, Hung-Lin Chen, Tian Sheng Lin
  • Publication number: 20100247100
    Abstract: A method for receiving an optical orthogonal frequency-division multiplexing (OFDM) signal and a receiver thereof are applicable to an optical OFDM system. The receiving method includes the following steps. An optical signal is converted into a digital signal. A symbol boundary of the digital signal is estimated. A guard interval of the digital signal is removed according to the symbol boundary, so as to generate an electrical signal. The electrical signal is converted into a plurality of frequency domain sub-carriers in a fast Fourier transform (FFT) manner. A timing offset is estimated with pilot carriers and frequency domain sub-carriers corresponding to the same symbol period. The estimated symbol boundary is compensated with the timing offset. Each frequency domain sub-carrier includes a plurality of pilot carrier signals. Through the receiving method, the timing offset arisen from chromatic dispersion of an optical fiber is effectively estimated and adopted for compensation.
    Type: Application
    Filed: May 12, 2009
    Publication date: September 30, 2010
    Applicant: Industrial Technology Research Institute
    Inventors: Yu Min Lin, Dar Zu Hsu, Hung Lin Chen
  • Publication number: 20100169402
    Abstract: An FFT processor is disclosed, which includes a first multi-pipelined MDC unit, a second multi-pipelined MDC unit and a switching network. The first multi-pipelined MDC unit and the second multi-pipelined MDC unit respectively employ a plurality of MDC circuits to change the positions of the delayers thereof in parallel way. By changing the operation time sequence of the signals in the first multi-pipelined MDC unit and the second multi-pipelined MDC unit, the first multi-pipelined MDC unit is able to directly send the operation results to the second multi-pipelined MDC unit through the switching network.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 1, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hung-Lin Chen, Yu-Min Lin, Dar-Zu Hsu, Yuan Chen, Chen-Yi Lee
  • Publication number: 20100086994
    Abstract: A fermentation apparatus includes a fermentation tank, an air-hole mesh board, a lift-up cover, a blender and a pressurization equipment. An opening is above fermentation tank, an oblique-board base is at the bottom of the fermentation tank, and a feed opening and an air outlet are on the fermentation tank. Two air inlet holes are on the oblique-board base to form a passage through the oblique-board base. Exhaustion holes are on a surface of the oblique-board base and interconnected with the passage. The air-hole mesh board is installed in the fermentation tank and between the feed opening and the oblique-board base. The lift-up cover is connected to the fermentation tank and disposed above the fermentation tank for covering the opening. The blender is between the lift-up cover and the air-hole mesh board. The pressurization equipment is connected to the air inlet hole for supplying a high-pressure gas into fermentation tank.
    Type: Application
    Filed: October 7, 2008
    Publication date: April 8, 2010
    Applicant: TCI CO., LTD.
    Inventors: Yung-Hsiang Lin, Hung-Lin Chen
  • Publication number: 20100013059
    Abstract: The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 21, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chang Hsieh, Hung-Lin Chen, Hsiu-Mei Yu, Chin Kun Lan, Dong-Lung Lee