Abstract: An electrothermal module includes a first conductive layer, a second conductive layer, and a heat generating layer. The first conductive layer and the second conductive layer respectively include silver metal. The heat generating layer has a first portion, the first portion is disposed between the first conductive layer and the second conductive layer to form an electrothermal conversion portion of the electrothermal module, and the heat generating layer includes a conductive carbon material.

Abstract: A vacuum apparatus includes process chambers, and a transfer chamber coupled to the process chambers. The transfer chamber includes one or more vacuum ports, thorough which a gas inside the transfer chamber is exhausted, and vent ports, from which a vent gas is supplied. The one or more vacuum ports and the vent ports are arranged such that air flows from at least one of the vent ports to the one or more vacuum ports are line-symmetric with respect to a center line of the transfer chamber.

Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.

Abstract: Methods of amplifying and determining a target nucleotide sequence are provided. The method of amplifying the target nucleotide sequence includes the following steps. A first adaptor and a second adaptor are linked to two ends of a double-stranded nucleic acid molecule with a target nucleotide sequence respectively to form a nucleic acid template, in which the first adaptor includes a Y-form adaptor or a hairpin adaptor and the second adaptor is a hairpin adaptor. Then, a PCR amplification cycle is performed on the nucleic acid template to obtain a PCR amplicon of the target nucleotide sequence.

Abstract: An engaging mechanism includes a casing, a first engaging member and a second engaging member. The casing has a first engaging recess and a second engaging recess. The first engaging member is slidably disposed in the casing and has a first engaging portion. The second engaging member is rotatably disposed in the casing and has a second engaging portion. When the first engaging member is located at a first lock position, the second engaging member is able to rotate between a second lock position and a second unlock position. When the second engaging member is located at the second unlock position and the first engaging member slides from the first lock position to a first unlock position, the first engaging member pushes the second engaging member to rotate toward the second lock position, such that the second engaging portion blocks the second engaging recess.

Abstract: A handle module applicable to a server or a server system is provided. The handle module includes a handle and a plate. The handle includes a sliding column assembly. The plate includes a first sliding rail and a second sliding rail. The sliding column assembly is pivotably and slidably disposed in the first sliding rail and the second sliding rail. A user pushes the handle to install the server in a rack.

Abstract: A handle module applicable to a server or a server system is provided. The handle module includes a handle and a plate. The handle includes a sliding column assembly. The plate includes a first sliding rail and a second sliding rail. The sliding column assembly is pivotably and slidably disposed in the first sliding rail and the second sliding rail. A user pushes the handle to install the server in a rack.

Abstract: A chassis includes a housing, a partition, a movable member and a tray. The housing includes a top plate and a bottom plate, and the top plate is opposite to the bottom plate. An accommodating space is located between the top plate and the bottom plate. The bottom plate has a through hole. The partition is disposed in the accommodating space. The movable member is connected to the partition. The movable member is configured to move between a first position and a second position. The tray includes a latch member. When the movable member is located at the first position and the tray is placed into the accommodating space, the movable member is embedded into the through hole and the latch member engages with the movable member. When the movable member is located at the second position, the movable member disengages from the through hole.

Abstract: An equipment rack includes two rack rails and a bracket. The bracket includes a bracket body and a first and a second connection device disposed at the bracket body's ends. The first connection device includes a rod part extending outward relative to the bracket body. An engaging section and a supporting section are formed on the rod part in the extending direction of the rod part. The engaging section is between the supporting section and the bracket body. The bracket is installed on one rack rail by the supporting section being inserted into a hole of said rack rail and is installed on the other rack rail by the second connection device engaging with the other rack rail. The bracket body is operable to move relative to the rack rails so that the engaging section enters the hole and the second connection device is disengaged from the rack rail.

Abstract: A method of determining if a layout design for fabricating a layer of features of an integrated circuit is N-colorable, comprising identifying a set of candidate cells among layout cells of a layout design. Each candidate cell of the set of candidate cells is one of the set of base layout cells, or one of the set of composite layout cells, and constituent layout cells of the one of the set of composite layout cells having been determined as N-colorable. Whether a first candidate cell of the set of candidate cell is N-colorable is determined. An abutment-sensitive conflict graph of the first candidate cell is generated when the first candidate cell is N-colorable and the first candidate cell is not the top layout cell.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.

Abstract: An equipment rack includes two rack rails and a bracket . The bracket includes a bracket body and a first and a second connection member disposed at the bracket body's ends. The first connection member includes a rod part extending outward relative to the bracket body. An engaging section and a supporting section are formed on the rod part in the extending direction of the rod part . The engaging section is between the supporting section and the bracket body. The bracket is installed on one rack rail by the supporting section being inserted into a hole of said rack rail and is installed on the other rack rail by the second connection member engaging with the other rack rail. The bracket body is operable to move relative to the rack rails so that the engaging section enters the hole and the second connection member is disengaged from the rack rail.

Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.

Abstract: A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC.

Abstract: A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing.

Abstract: A drawer and a server using the same are provided. The drawer is configured for a node of a server. The drawer includes a bottom plate and a bezel. The bottom plate is configured for disposing a circuit board. The bezel is disposed at one side of the bottom plate. The bezel includes a body and a door structure connected to the body. The door structure can be opened to open an opening, such that the node is accessible through the opening. The door structure can be closed to shut the opening, such that the bezel works as an electrostatic shield of the circuit board.