Abstract: Methods and arrangements for a low power, phase-locked loop (PLL) are disclosed. Embodiments include a multi-phase oscillator like a voltage-controlled oscillator (VCO) to generate multiple phases of a clock signal. The multiple phases are then combined to generate a single clock signal having a frequency substantially equivalent to the number of phases multiplied by the frequency of the clock signal generated by the multi-phase VCO. Advantageously, embodiments can generate clock signals having frequencies that are multiples of the frequency generated by the VCO, reducing the power consumed by the VCO to produce a clock signal having the same frequency as a clock signal generated by a single phase VCO. Further, the achievable frequency for the VCO is increased. In many embodiments, a high speed, n-bit frequency divider that implements a pulse latch facilitates the use of the multi-phase VCO to generate the very high frequency clock signals.

Abstract: The N channel field effect transistor (NFET) of the inverting output stage of a LSDL gate is split into a large NFET and a small NFET. The large NFET is coupled to a feedforward pulse so that it is turned ON only when the inverting output is a logic one. When the inverting output is a logic one, another inverting stage turns ON if the dynamic node evaluates to a logic zero. The dynamic node is inverted and coupled to the large NFET on the inverting output stage thus quickly pulling the inverting output to a logic zero. The small NFET is turned ON as a keeper device through the normal logic path. If the inverting data output is a logic zero the feedforward pulse is not generated. By making the largest NFET a pulsed device the other FETs are reduced in size resulting in leakage and switching power savings.

Abstract: An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.

Abstract: A VCO is configured using a ring oscillator with voltage controlled feedforward inverting stages coupled around the inverting stages making up the basic ring oscillator to enable the frequency of the ring oscillator to be voltage controlled. A latch and multiplexer is used to select between two or more outputs within the ring oscillator to change the basic frequency range of the VCO glitch free. To achieve a wide range VCO, additional stages are added to the basic ring oscillator. When the number of stages is an odd number greater than seven, then the voltage controlled feedforward inverting stages feedback to the outputs of the first and second inverting stages of the ring oscillator. Two additional multiplexers are added to select which feedforward inverting stage is coupled to the first and second inverting stage. This allows a wide range interleaved VCO that switches between frequency ranges glitch free.

Abstract: A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k?1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k?1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k?1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k?1.

Abstract: A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.

Abstract: A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.

Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.

Abstract: A preferred embodiment of a guide boot for a fiber-optic cable mechanically coupled to a connector comprises a mating portion having an interior surface defining a passage for receiving a portion of the connector and the fiber-optic cable, and a plurality of ribs formed on the interior surface and extending along at least a portion of a length of the mating portion. A preferred embodiment of a guide boot also comprises a body portion adjoining the mating portion and having an interior surface that defines a passage for receiving the fiber-optic cable. The interior surface of the body portion is curved so that the body portion bends the fiber-optic cable.

Abstract: An LSDL circuit has both an output and a complementary output generated by inverting the output with an inverter logic gate. A keeper PFET is added by coupling its drain terminal to the dynamic node. The keeper PFET has its source terminal coupled to the positive power supply voltage and its gate terminal coupled to the complementary output. The output and the dynamic node may both be at a logic one when the output is a logic one from the previous evaluation cycle and the dynamic node is precharged. In this case, the complementary output is a logic zero which turns ON the keeper PFET and reinforces the precharge on the dynamic node. When the output is evaluating to a logic zero, the output will transition quickly to a logic zero. If the output is transitioning from a logic zero to a logic one, then the keeper PFET is OFF and does not affect the dynamic node.

Abstract: LSDL logic is provided with circuitry that has logic controls to provide two modes of operation. The half latch and the PFET that normally forms the keeper function on the dynamic node are modified. The inverter function of the series connected PFET and NFET have their corresponding positive and negative power supply terminals coupled to logic gates. In this way, the inverter may be turned ON so that the half latch functions as a keeper or it may be turned OFF to remove it from operating at all in the mode where the LSDL logic circuit needs to operate with a fast pulse clock. Likewise, the positive supply voltage may be removed while allowing the NFET device to operate to turn ON the PFET pull-up device for burn-in operation.

Abstract: An electrical connector including a frame, electrical contacts, and a system for retaining and ejecting an electronic module. The frame has a receiving area which is sized and shaped to removably received an end of at least one electronic module. The electrical contacts are connected to the frame. The contacts include spring contacts adapted to make removable connection to contact pads on the end of the electronic module at a first inserted position. The system for retaining and ejecting includes springs adapted to push on the end of the electronic module when the module is moved past the first inserted position. When the electronic module is inserted into the frame the contacts are adapted to make electrical connection with the contact pads on the end of the electronic module before the electronic module moves the springs.

Abstract: A monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), a polysilicon resistor (58), and an inductor (155), and an ESD protection device (160). A first P.sup.+ sinker (28) provides signal isolation between two FETs (113, 115) separated by the first sinker (28) and is coupled to a source region (86) of a power FET (115) via a self-aligned titanium silicide structure (96). A second P.sup.+ sinker (29) is coupled to a bottom plate (44) of the double polysilicon capacitor (57). A third P+ sinker (178) is coupled to a source region (168) of the ESD protection device (160) via another titanium silicide structure (174).