Patents by Inventor Hung-Pin Chang
Hung-Pin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991485Abstract: A projection apparatus including a projection device, a reflecting component, and an image capturing device is provided. The projection device is adapted to project an image light beam to form a projection image. The reflecting component is disposed on the projection device and has a reflecting surface. The image capturing device is disposed on the projection device and has an image capturing end. The image capturing end faces the reflecting surface. The reflecting surface is adapted to reflect the projection image to the image capturing end.Type: GrantFiled: July 12, 2022Date of Patent: May 21, 2024Assignee: Coretronic CorporationInventors: Jen-Yu Shie, Kuang-Hsiang Chang, Hung-Pin Chen, Heng Li
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Publication number: 20240130257Abstract: Devices and method for forming a switch including a heater layer including a first heater pad, a second heater pad, and a heater line connecting the first heater pad and the second heater pad, a phase change material (PCM) layer positioned in a same vertical plane as the heater line, and a floating spreader layer including a first portion positioned in the same vertical plane as the heater line and the PCM layer, in which the first portion has a first width that is less than or equal to a distance between proximate sidewalls of the first heater pad and the second heater pad.Type: ApplicationFiled: April 21, 2023Publication date: April 18, 2024Inventors: Fu-Hai LI, Yi Ching ONG, Hsin Heng WANG, Tsung-Hao YEH, Yu-Wei TING, Kuo-Pin CHANG, Hung-Ju LI, Kuo-Ching HUANG
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Publication number: 20240128218Abstract: A semiconductor package includes a first semiconductor substrate, an array of conductive bumps, a second semiconductor substrate, and a spacing pattern. The first semiconductor substrate includes a pad region and an array of first pads disposed within the pad region. The array of conductive bumps is disposed on the array of first pads respectively. The second semiconductor substrate is disposed over the first semiconductor substrate and includes an array of second pads bonded to the array of conductive bumps respectively. The spacing pattern is disposed between the first semiconductor substrate and the second semiconductor substrate, wherein the spacing pattern is located at a periphery of the pad region.Type: ApplicationFiled: January 19, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Wei-Cheng Wu, Ming-Shih Yeh, An-Jhih Su, Der-Chyang Yeh
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Publication number: 20240071947Abstract: A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Yu-Ling Tsai, Lai Wei Chih, Meng-Tsan Lee, Hung-Pin Chang, Li-Han Hsu, Chien-Chia Chiu, Cheng-Hung Lin
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Publication number: 20240063030Abstract: Provided is a semiconductor device including a substrate, an interconnect structure, a first passivation layer, a stress buffer layer, a pad structure, and a second passivation layer. The interconnect structure is disposed on the substrate. The first passivation layer and the stress buffer layer are disposed on the interconnect structure. The pad structure includes: a lower portion embedded in the first passivation layer and the stress buffer layer, and laterally wrapped by the first passivation layer and the stress buffer layer; and an upper portion on the lower portion. The upper portion has a periphery laterally offset outward from a periphery of the lower portion, so that a bottom surface of the upper portion contacts a top surface of the stress buffer layer. The second passivation layer is disposed on the stress buffer layer and laterally wraps the upper portion of the upper portion of the pad structure.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Han-Yi Lu, Wei-Cheng Wu, Der-Chyang Yeh
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Publication number: 20230402429Abstract: Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.Type: ApplicationFiled: January 9, 2023Publication date: December 14, 2023Inventors: Chien-Fu Tseng, Yu Chieh Yung, Cheng-Hsien Hsieh, Hung-Pin Chang, Li-Han Hsu, Wei-Cheng Wu, Der-Chyang Yeh
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Patent number: 11688639Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.Type: GrantFiled: December 16, 2019Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
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Publication number: 20230197464Abstract: A manufacturing method of a through substrate via includes at least the following steps. A protective liner is formed within an opening of a dielectric layer, where the opening exposes a portion of a semiconductor substrate underlying the dielectric layer. The portion of the semiconductor substrate is removed through the opening, where an overhang portion is formed at a top edge of the semiconductor substrate and masked by the protective liner after the removing. The overhang portion of the semiconductor substrate, the protective liner, and a portion of the dielectric layer adjoining the protective liner is removed to form a via hole. A conductive material is formed in the via hole.Type: ApplicationFiled: February 13, 2023Publication date: June 22, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Publication number: 20230069214Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 11594420Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A patterned mask layer with a first opening is formed on a dielectric layer overlying a semiconductor substrate. A portion of the dielectric layer accessibly exposed by the first opening of the patterned mask layer is removed to form a second opening. A first protective film is formed on inner sidewalls of the dielectric layer and the patterned mask layer, where the second opening and the first protective film are formed at the same step. A second protective film is formed on the first protective film to form a protective structure covering the inner sidewalls. A portion of the semiconductor substrate accessibly exposed by the second opening is removed to form a via hole including an undercut underlying the protective structure. The via hole is trimmed and a through substrate via is formed in the via hole.Type: GrantFiled: August 30, 2021Date of Patent: February 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Tsang-Jiuh Wu, Wen-Chih Chiou
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Patent number: 11004832Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.Type: GrantFiled: December 19, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
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Patent number: 10978346Abstract: An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.Type: GrantFiled: September 13, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hui Huang, Hung-Pin Chang, Sao-Ling Chiu, Shang-Yun Hou, Wan-Yu Lee
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Publication number: 20200126953Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
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Publication number: 20200118879Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
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Publication number: 20200006143Abstract: An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Sung-Hui Huang, Hung-Pin Chang, Sao-Ling Chiu, Shang-Yun Hou, Wan-Yu Lee
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Patent number: 10515933Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.Type: GrantFiled: March 21, 2017Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
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Patent number: 10510603Abstract: An embodiment method includes bonding a first die to a first side of an interposer, the interposer comprising a substrate; after bonding the first die to the first side of the interposer, depositing a first insulating layer on a second side of the interposer opposite the first side; patterning an opening through the substrate and the first insulating layer; and depositing a second insulating layer over the first insulating layer and along sidewalls and a lateral surface of the opening. The second insulating layer comprises silicon. The method further includes removing lateral portions of the second insulating layer to define a sidewall spacer on sidewalls of the opening and forming a through via in the opening, wherein the through via is electrically connected to the first die.Type: GrantFiled: November 1, 2017Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Hui Huang, Hung-Pin Chang, Sao-Ling Chiu, Shang-Yun Hou, Wan-Yu Lee
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Patent number: 10510604Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.Type: GrantFiled: December 19, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
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Patent number: 10497619Abstract: A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the openings. A thickness of the substrate may be reduced from a second surface of the substrate, opposite the first surface, to a third surface opposite the first surface which exposes the conductive material in the first opening and the conductive material in the second opening. A light emitting diode (LED) device is connected to the third surface of the substrate.Type: GrantFiled: August 10, 2018Date of Patent: December 3, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chia-Lin Yu, Hung-Pin Chang, Chien Ling Hwang, Jui-Pin Hung, Yung-Chi Lin
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Publication number: 20190122930Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.Type: ApplicationFiled: December 19, 2018Publication date: April 25, 2019Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou